Re: [PATCH] mtd: spinand: macronix: Add support for serial NAND flash
Hi Miquel,
"Miquel Raynal" wrote on 2021/05/27 下午
04:58:45:
> "Miquel Raynal"
> 2021/05/27 下午 04:59
>
> To
>
> "Jaime Liao" ,
>
> cc
>
> u-boot@lists.denx.de, ja...@amarulasolutions.com, vigne...@ti.com,
> zhengxu...@mxic.com.tw, ycl...@mxic.com.tw
>
> Subject
>
> Re: [PATCH] mtd: spinand: macronix: Add support for serial NAND flash
>
> Hi Jaime,
>
> Jaime Liao wrote on Thu, 27 May 2021 16:51:12
> +0800:
>
> > Macronix NAND Flash devices are available in different configurations
> > and densities.
> >
> > MX"35" means SPI NAND
> > MX35"LF"/"UF" , LF means 3V and UF meands 1.8V
> > MX35LF"2G" , 2G means 2Gbits
> > MX35LF2G"E4"/"24"/"14",
> > E4 means internal ECC and Quad I/O(x4)
> > 24 means 8-bit ecc requirement and Quad I/O(x4)
> > 14 means 4-bit ecc requirement and Quad I/O(x4)
> >
> > MX35LF2G14AC is 3V 2Gbit serial NAND flash device
> > (without on-die ECC)
> > https://www.mxic.com.tw/Lists/Datasheet/Attachments/7926/
> MX35LF2G14AC,%203V,%202Gb,%20v1.1.pdf
> >
> > MX35UF4G24AD/MX35UF2G24AD/MX35UF1G24AD is 1.8V 4Gbit serial NAND
> flash device
> > (without on-die ECC)
> > https://www.mxic.com.tw/Lists/Datasheet/Attachments/7980/
> MX35UF4G24AD,%201.8V,%204Gb,%20v0.00.pdf
> >
> > MX35UF4GE4AD/MX35UF2GE4AD/MX35UF1GE4AD are 1.8V 4G/2Gbit serial
> > NAND flash device with 8-bit on-die ECC
> > https://www.mxic.com.tw/Lists/Datasheet/Attachments/7983/
> MX35UF4GE4AD,%201.8V,%204Gb,%20v0.00.pdf
> >
> > MX35UF2GE4AC/MX35UF1GE4AC are 1.8V 2G/1Gbit serial
> > NAND flash device with 8-bit on-die ECC
> > https://www.mxic.com.tw/Lists/Datasheet/Attachments/7974/
> MX35UF2GE4AC,%201.8V,%202Gb,%20v1.0.pdf
> >
> > MX35UF2G14AC/MX35UF1G14AC are 1.8V 2G/1Gbit serial
> > NAND flash device (without on-die ECC)
> > https://www.mxic.com.tw/Lists/Datasheet/Attachments/7931/
> MX35UF2G14AC,%201.8V,%202Gb,%20v1.1.pdf
> >
> > Validated via normal(default) and QUAD mode by read, erase, read back,
> > on Xilinx Zynq PicoZed FPGA board which included Macronix
> > SPI Host(drivers/spi/spi-mxic.c).
> >
> > Signed-off-by: Jaime Liao
> > ---
> > drivers/mtd/nand/spi/macronix.c | 100 +++
> +
> > 1 file changed, 100 insertions(+)
> >
> > diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/
> spi/macronix.c
> > index 215f09a..8a33dce 100644
> > --- a/drivers/mtd/nand/spi/macronix.c
> > +++ b/drivers/mtd/nand/spi/macronix.c
> > @@ -114,6 +114,106 @@ static const struct spinand_info
> macronix_spinand_table[] = {
> > _cache_variants),
> > SPINAND_HAS_QE_BIT,
> > SPINAND_ECCINFO(_ooblayout, NULL)),
> > + SPINAND_INFO("MX35LF2G14AC", 0x20,
> > + NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),
> > + NAND_ECCREQ(4, 512),
> > + SPINAND_INFO_OP_VARIANTS(_cache_variants,
> > + _cache_variants,
> > + _cache_variants),
> > + SPINAND_HAS_QE_BIT,
> > + SPINAND_ECCINFO(_ooblayout,
> > + mx35lf1ge4ab_ecc_get_status)),
>
> This looks like a copy of your previous patch, with the SPINAND_ID
> macro dropped.
>
> It would be great if you could clarify your intentions when sending
> patches. This means:
> - Counting up patch versions
> - Explaining their differences and why
>
> So, what is the purpose of this patch give the fact that I already
> applied one very similar yesterday?
>
> Thanks,
> Miquèl
Forward my colleague(Jaime)'s mail as below:
"It is grateful for your comments.
Two patches are different for linux kernel and u-boot.
In this u-boot patch, my purpose is add SPI-NAND IDs in u-boot.
For patching reasonable, I have a question.
AFAIK u-boot didn't include sw-ecc engine.
Is it suitable for Flash which are sw-ecc requirement?"
Thanks,
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=
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Re: [Patch v2 1/2] clk: zynq: Add clock wizard driver
Hi Michal,
Thank you for your review.
> On 4/29/21 11:31 AM, Zhengxun Li wrote:
> > The Clocking Wizard IP supports clock circuits customized
> > to your clocking requirements. The wizard support for
> > dynamically reconfiguring the clocking primitives for
> > Multiply, Divide, Phase Shift/Offset, or Duty Cycle.
> >
> > Limited by uboot clk uclass without set_phase API, this
> > patch only provides set_rate to modify the frequency.
> >
> > Signed-off-by: Zhengxun Li
> > ---
> > drivers/clk/Kconfig | 9 +++
> > drivers/clk/Makefile| 1 +
> > drivers/clk/clk-xlnx-clock-wizard.c | 152 +++
> +
> > 3 files changed, 162 insertions(+)
> > create mode 100644 drivers/clk/clk-xlnx-clock-wizard.c
> >
> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> > index 4aeaa0c..f0d4fe0 100644
> > --- a/drivers/clk/Kconfig
> > +++ b/drivers/clk/Kconfig
> > @@ -136,6 +136,15 @@ config CLK_ZYNQMP
> > This clock driver adds support for clock realted settings for
> > ZynqMP platform.
> >
> > +config COMMON_CLK_XLNX_CLKWZRD
> > + bool "Xilinx Clocking Wizard"
> > + depends on CLK
> > + help
> > + Support for the Xilinx Clocking Wizard IP core clock generator.
> > + Adds support for clocking wizard and compatible.
> > + This driver supports the Xilinx clocking wizard programmable
clock
> > + synthesizer.
> > +
> > config CLK_STM32MP1
> > bool "Enable RCC clock driver for STM32MP1"
> > depends on ARCH_STM32MP && CLK
> > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> > index 645709b..f4ddbe8 100644
> > --- a/drivers/clk/Makefile
> > +++ b/drivers/clk/Makefile
> > @@ -43,6 +43,7 @@ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
> > obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
> > obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
> > obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
> > +obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
> > obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
> > obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
> > obj-$(CONFIG_SANDBOX) += clk_sandbox.o
> > diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/
> clk-xlnx-clock-wizard.c
> > new file mode 100644
> > index 000..55adb16
> > --- /dev/null
> > +++ b/drivers/clk/clk-xlnx-clock-wizard.c
> > @@ -0,0 +1,152 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Xilinx 'Clocking Wizard' driver
> > + *
> > + * Copyright (c) 2021 Macronix Inc.
> > + *
> > + * Author: Zhengxun Li
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#define SRR 0x0
> > +
> > +#define SR 0x4
> > +#define SR_LOCKED BIT(0)
> > +
> > +#define CCR(x) (0x200 + ((x) * 4))
> > +
> > +#define FBOUT_CFG CCR(0)
> > +#define FBOUT_DIV(x) (x)
> > +#define FBOUT_GET_DIV(x) ((x) & GENMASK(7, 0))
> > +#define FBOUT_MUL(x) ((x) << 8)
> > +#define FBOUT_GET_MUL(x) (((x) & GENMASK(15, 8)) >> 8)
> > +#define FBOUT_FRAC(x) ((x) << 16)
> > +#define FBOUT_GET_FRAC(x) (((x) & GENMASK(25, 16)) >> 16)
> > +#define FBOUT_FRAC_EN BIT(26)
> > +
> > +#define FBOUT_PHASE CCR(1)
> > +
> > +#define OUT_CFG(x) CCR(2 + ((x) * 3))
> > +#define OUT_DIV(x) (x)
> > +#define OUT_GET_DIV(x) ((x) & GENMASK(7, 0))
> > +#define OUT_FRAC(x) ((x) << 8)
> > +#define OUT_GET_FRAC(x) (((x) & GENMASK(17, 8)) >> 8)
> > +#define OUT_FRAC_EN BIT(18)
> > +
> > +#define OUT_PHASE(x) CCR(3 + ((x) * 3))
> > +#define OUT_DUTY(x) CCR(4 + ((x) * 3))
> > +
> > +#define CTRL CCR(23)
> > +#define CTRL_SEN BIT(2)
> > +#define CTRL_SADDR BIT(1)
> > +#define CTRL_LOAD BIT(0)
> > +
> > +/*
>
> /**
>
> > + * struct clkwzrd - Clock wizard private data structure
> > + *
> > + * @lock Lock pointer
>
> not listed below
>
> > + * @base Memory base
>
>
> > + * @vco_clk voltage-controlled oscillator frequency
Okay.
> > + */
> > +struct clkwzd {
> > + void __iomem *base;
> > + u64 vco_clk;
> > +};
> > +
> > +static int clk_wzrd_enable(struct clk *clk)
> > +{
> > + struct clkwzd *priv = dev_get_priv(clk->dev);
> > + int ret;
> > + u32 val;
> > +
> > + ret = readl_poll_sleep_timeout(priv->base + SR, val, val &
SR_LOCKED,
> > + 1, 100);
> > + if (!ret) {
> > + writel(CTRL_SEN | CTRL_SADDR | CTRL_LOAD, priv->base + CTRL);
> > + writel(CTRL_SADDR, priv->base + CTRL);
> > + ret = readl_poll_sleep_timeout(priv->base + SR, val,
> > + val & SR_LOCKED, 1, 100);
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static unsigned long clk_wzrd_set_rate(struct clk *clk, ulong rate)
> > +{
> > + struct clkwzd *priv = dev_get_priv(clk->dev);
> > + u64 div;
> > + u32 cfg;
> > +
> > + /* Get output clock divide value */
> > + div = DIV_ROUND_DOWN_ULL(priv->vco_clk * 1000, rate);
> > + if (div < 1000 || div > 255999)
> > + return
Re: [PATCH 1/2] clk: zynq: Add clock wizard driver
Hi, > On 4/7/21 11:05 AM, zhengxunli wrote: > > The Clocking Wizard IP supports clock circuits customized > > to your clocking requirements. The wizard support for > > dynamically reconfiguring the clocking primitives for > > Multiply, Divide, Phase Shift/Offset, or Duty Cycle. > > > > Limited by uboot clk uclass without set_phase API, this > > patch only provides set_rate to modify the frequency and > > set 50% duty cycle by default. > > > > Signed-off-by: zhengxunli > > Please use full name. Okay, got it. > > > --- > > drivers/clk/Kconfig | 7 ++ > > drivers/clk/Makefile | 1 + > > drivers/clk/clk_wizard.c | 180 ++ > + > > 3 files changed, 188 insertions(+) > > create mode 100644 drivers/clk/clk_wizard.c > > > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig > > index 4aeaa0c..4ebeccc 100644 > > --- a/drivers/clk/Kconfig > > +++ b/drivers/clk/Kconfig > > @@ -136,6 +136,13 @@ config CLK_ZYNQMP > > This clock driver adds support for clock realted settings for > > ZynqMP platform. > > > > +config CLK_WIZARD > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ > tree/drivers/staging/clocking-wizard/Kconfig?h=v5.12-rc6 > > Small alignment with kernel would be useful. > At least CLK_XLNX_CLKWZRD. > > > + bool "Enable clock wizard driver support for zynq" > > + depends on CLK && ARCH_ZYNQ > > Clocking wizard is standard PL based IP not just related to Zynq. It can > be used by Microblaze, ARM cores, etc. It means no need to have > dependency on ZYNQ here. > > > + help > > + This clock driver adds support for clock wizard setting for > > + Zynq platform. > > ditto > Okay, I will fix in the next version. > > + > > config CLK_STM32MP1 > > bool "Enable RCC clock driver for STM32MP1" > > depends on ARCH_STM32MP && CLK > > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile > > index 645709b..d8b878c 100644 > > --- a/drivers/clk/Makefile > > +++ b/drivers/clk/Makefile > > @@ -43,6 +43,7 @@ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ > > obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o > > obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o > > obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o > > +obj-$(CONFIG_CLK_WIZARD) += clk_wizard.o > > obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o > > obj-$(CONFIG_MACH_PIC32) += clk_pic32.o > > obj-$(CONFIG_SANDBOX) += clk_sandbox.o > > diff --git a/drivers/clk/clk_wizard.c b/drivers/clk/clk_wizard.c > > new file mode 100644 > > index 000..f5c2387 > > --- /dev/null > > +++ b/drivers/clk/clk_wizard.c > > name could be also aligned with kernel to have easier match with the kernel. Okay, got it. > > > @@ -0,0 +1,180 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Xilinx 'Clocking Wizard' driver > > + * > > + * Copyright (c) 2021 Macronix Inc. > > + * > > + * Author: Zhengxun Li > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#define SRR 0x0 > > + > > +#define SR 0x4 > > +#define SR_LOCKED BIT(0) > > + > > +#define CCR(x) (0x200 + ((x) * 4)) > > + > > +#define FBOUT_CFG CCR(0) > > +#define FBOUT_DIV(x) (x) > > +#define FBOUT_GET_DIV(x) ((x) & GENMASK(7, 0)) > > +#define FBOUT_MUL(x) ((x) << 8) > > +#define FBOUT_GET_MUL(x) (((x) & GENMASK(15, 8)) >> 8) > > +#define FBOUT_FRAC(x) ((x) << 16) > > +#define FBOUT_GET_FRAC(x) (((x) & GENMASK(25, 16)) >> 16) > > +#define FBOUT_FRAC_EN BIT(26) > > + > > +#define FBOUT_PHASE CCR(1) > > + > > +#define OUT_CFG(x) CCR(2 + ((x) * 3)) > > +#define OUT_DIV(x) (x) > > +#define OUT_GET_DIV(x) ((x) & GENMASK(7, 0)) > > +#define OUT_FRAC(x) ((x) << 8) > > +#define OUT_GET_FRAC(x) (((x) & GENMASK(17, 8)) >> 8) > > +#define OUT_FRAC_EN BIT(18) > > + > > +#define OUT_PHASE(x) CCR(3 + ((x) * 3)) > > +#define OUT_DUTY(x) CCR(4 + ((x) * 3)) > > + > > +#define CTRL CCR(23) > > +#define CTRL_SEN BIT(2) > > +#define CTRL_SADDR BIT(1) > > +#define CTRL_LOAD BIT(0) > > + > > +/* > > /** for kernel-doc as noted below. > > > + * MMCM Block
Re: [PATCH 2/2] board: Add Zynq Mxic picozed development board support
Hi Michal,
Thank you for your quick reply!
"Michal Simek" wrote on 2021/04/07 下午
08:35:18:
> "Michal Simek"
> 2021/04/07 下午 08:35
>
> To
>
> "zhengxunli" , ,
>
> cc
>
> , ,
>
> Subject
>
> Re: [PATCH 2/2] board: Add Zynq Mxic picozed development board support
>
> Hi,
>
> On 4/7/21 11:05 AM, zhengxunli wrote:
> > Add the Zynq Mxic picozed development board support.
> >
> > Signed-off-by: zhengxunli
> > ---
> > arch/arm/dts/Makefile | 3 +-
> > arch/arm/dts/zynq-mxic-picozed.dts | 66 +
> +
> > 2 files changed, 68 insertions(+), 1 deletion(-)
> > create mode 100644 arch/arm/dts/zynq-mxic-picozed.dts
> >
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index 9a8de46..059bb3b 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -286,7 +286,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
> > zynq-zturn.dtb \
> > zynq-zturn-v5.dtb \
> > zynq-zybo.dtb \
> > - zynq-zybo-z7.dtb
> > + zynq-zybo-z7.dtb \
> > + zynq-mxic-picozed.dtb
> > dtb-$(CONFIG_ARCH_ZYNQMP) += \
> > avnet-ultra96-rev1.dtb \
> > avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \
> > diff --git a/arch/arm/dts/zynq-mxic-picozed.dts b/arch/arm/dts/
> zynq-mxic-picozed.dts
> > new file mode 100644
> > index 000..d2ff358
> > --- /dev/null
> > +++ b/arch/arm/dts/zynq-mxic-picozed.dts
> > @@ -0,0 +1,66 @@
> > +/dts-v1/;
> > +/include/ "zynq-7000.dtsi"
> > +
> > +/ {
> > + model = "Zynq MXIC PicoZed Development Board";
> > + compatible = "mxicy,zynq-mxic-picozed", "xlnx,zynq-7000";
> > +
> > + aliases {
> > + ethernet0 =
> > + serial0 =
> > + spi0 = _controller;
> > + };
> > +
> > + memory@0 {
> > + device_type = "memory";
> > + reg = <0x0 0x3000>;
> > + };
> > +
> > + chosen {
> > + bootargs = "";
> > + stdout-path = "serial0:115200n8";
> > + };
> > +};
> > +
> > + {
> > + clkwizard: clkwizard@43c2 {
> > + compatible = "xlnx,clk-wizard-5.1";
> > + reg = <0x43c2 0x1>;
> > + clocks = < 18>, < 18>;
> > + clock-names = "aclk", "clk_in1";
> > + #clock-cells = <1>;
> > + clock-frequency = <13330>;
> > + xlnx,clk-wizard-num-outputs = <2>;
> > + };
>
> This is definitely PL IP.
What is the PL?
> > +
> > + spi_controller: spi@43c3 {
> > + compatible = "mxicy,mx25f0a-spi";
>
>
> And I expect this is also PL based IP.
> And we have agreement that for upstream project we won't be accepting
> any description for PL.
> But there is not a problem with accepting driver for clocking wizard or
> this IP.
It sounds like we can move on.
> And picozed board is already supported in u-boot.
Thanks,
Zhengxun
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well as its attachment(s) from your system. In addition, please be
informed that collection, processing, and/or use of personal data is
prohibited unless expressly permitted by personal data protection laws.
Thank you for your attention and cooperation.
Macronix International Co., Ltd.
=
CONFIDENTIALITY NOTE:
This e-mail and any attachments may contain confidential information
and/or personal data, which is protected by applicable laws. Please be
reminded that duplication, disclosure, distribution, or use of this e-mail
(and/or its attachments) or any part thereof is prohibited. If you receive
this e-mail in error, please notify us immediately and delete this mail as
well as its attachment(s) from your system. In addition, please be
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prohibited unless expressly permitted by personal data protection laws.
Thank you for your attention and cooperation.
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=
==
[PATCH 2/2] board: Add Zynq Mxic picozed development board support
Add the Zynq Mxic picozed development board support.
Signed-off-by: zhengxunli
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/zynq-mxic-picozed.dts | 66 ++
2 files changed, 68 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/zynq-mxic-picozed.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9a8de46..059bb3b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -286,7 +286,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zturn.dtb \
zynq-zturn-v5.dtb \
zynq-zybo.dtb \
- zynq-zybo-z7.dtb
+ zynq-zybo-z7.dtb \
+ zynq-mxic-picozed.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
avnet-ultra96-rev1.dtb \
avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb\
diff --git a/arch/arm/dts/zynq-mxic-picozed.dts
b/arch/arm/dts/zynq-mxic-picozed.dts
new file mode 100644
index 000..d2ff358
--- /dev/null
+++ b/arch/arm/dts/zynq-mxic-picozed.dts
@@ -0,0 +1,66 @@
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+ model = "Zynq MXIC PicoZed Development Board";
+ compatible = "mxicy,zynq-mxic-picozed", "xlnx,zynq-7000";
+
+ aliases {
+ ethernet0 =
+ serial0 =
+ spi0 = _controller;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x3000>;
+ };
+
+ chosen {
+ bootargs = "";
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ {
+ clkwizard: clkwizard@43c2 {
+ compatible = "xlnx,clk-wizard-5.1";
+ reg = <0x43c2 0x1>;
+ clocks = < 18>, < 18>;
+ clock-names = "aclk", "clk_in1";
+ #clock-cells = <1>;
+ clock-frequency = <13330>;
+ xlnx,clk-wizard-num-outputs = <2>;
+ };
+
+ spi_controller: spi@43c3 {
+ compatible = "mxicy,mx25f0a-spi";
+ reg = <0x43c3 0x1>;
+ reg-names = "regs";
+ clocks = < 0>, < 1>, < 18>;
+ clock-names = "send_clk", "send_dly_clk", "ps_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <2500>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+ };
+};
+
+ {
+ ps-clk-frequency = <>;
+};
+
+ {
+ status = "okay";
+ phy-mode = "rgmii-id";
+};
+
+ {
+ status = "okay";
+};
--
1.9.1
[PATCH 1/2] clk: zynq: Add clock wizard driver
The Clocking Wizard IP supports clock circuits customized
to your clocking requirements. The wizard support for
dynamically reconfiguring the clocking primitives for
Multiply, Divide, Phase Shift/Offset, or Duty Cycle.
Limited by uboot clk uclass without set_phase API, this
patch only provides set_rate to modify the frequency and
set 50% duty cycle by default.
Signed-off-by: zhengxunli
---
drivers/clk/Kconfig | 7 ++
drivers/clk/Makefile | 1 +
drivers/clk/clk_wizard.c | 180 +++
3 files changed, 188 insertions(+)
create mode 100644 drivers/clk/clk_wizard.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4aeaa0c..4ebeccc 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -136,6 +136,13 @@ config CLK_ZYNQMP
This clock driver adds support for clock realted settings for
ZynqMP platform.
+config CLK_WIZARD
+ bool "Enable clock wizard driver support for zynq"
+ depends on CLK && ARCH_ZYNQ
+ help
+ This clock driver adds support for clock wizard setting for
+ Zynq platform.
+
config CLK_STM32MP1
bool "Enable RCC clock driver for STM32MP1"
depends on ARCH_STM32MP && CLK
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 645709b..d8b878c 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
+obj-$(CONFIG_CLK_WIZARD) += clk_wizard.o
obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
diff --git a/drivers/clk/clk_wizard.c b/drivers/clk/clk_wizard.c
new file mode 100644
index 000..f5c2387
--- /dev/null
+++ b/drivers/clk/clk_wizard.c
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx 'Clocking Wizard' driver
+ *
+ * Copyright (c) 2021 Macronix Inc.
+ *
+ * Author: Zhengxun Li
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define SRR0x0
+
+#define SR 0x4
+#define SR_LOCKED BIT(0)
+
+#define CCR(x) (0x200 + ((x) * 4))
+
+#define FBOUT_CFG CCR(0)
+#define FBOUT_DIV(x) (x)
+#define FBOUT_GET_DIV(x) ((x) & GENMASK(7, 0))
+#define FBOUT_MUL(x) ((x) << 8)
+#define FBOUT_GET_MUL(x) (((x) & GENMASK(15, 8)) >> 8)
+#define FBOUT_FRAC(x) ((x) << 16)
+#define FBOUT_GET_FRAC(x) (((x) & GENMASK(25, 16)) >> 16)
+#define FBOUT_FRAC_EN BIT(26)
+
+#define FBOUT_PHASECCR(1)
+
+#define OUT_CFG(x) CCR(2 + ((x) * 3))
+#define OUT_DIV(x) (x)
+#define OUT_GET_DIV(x) ((x) & GENMASK(7, 0))
+#define OUT_FRAC(x)((x) << 8)
+#define OUT_GET_FRAC(x)(((x) & GENMASK(17, 8)) >> 8)
+#define OUT_FRAC_ENBIT(18)
+
+#define OUT_PHASE(x) CCR(3 + ((x) * 3))
+#define OUT_DUTY(x)CCR(4 + ((x) * 3))
+
+#define CTRL CCR(23)
+#define CTRL_SEN BIT(2)
+#define CTRL_SADDR BIT(1)
+#define CTRL_LOAD BIT(0)
+
+/*
+ *MMCM Block Diagram
+ *
+ *++ +-+
+ * input ->| vco_clk_div_hw |->| vco_clk_mul_hw |--+
+ * rate| (int divide) | | (frac multiply) | |
+ *++ +-+ |
+ * |
+ * +VCO-rate---+
+ * |
+ * | ++
+ * +->| clkout[0] |-> output0 rate
+ * | | (frac divide) |
+ * | ++
+ * |
+ * | ++
+ * +->| clkout[1] |-> output1 rate
+ * | | (int divide) |
+ * | ++
+ * |
+ * ...
+ * |
+ * | ++
+ * +->| clkout[1] |-> output6 rate
+ *| (int divide) |
+ *++
+ *
+ * struct clkwzrd - Clock wizard private data structure
+ *
+ * @lock Lock pointer
+ * @base Memory base
+ * @vco_clkvoltage-controlled oscillator frequency
+ */
+struct clkwzd {
+ struct mutex lock;
+ void __iomem *base;
+ u64 vco_clk;
+};
+
+static int zynq_clk_wizard_enable(struct clk *clk)
+{
+ struct clkwzd *priv = dev_get_priv(clk->dev);
+ int ret;
+ u32 val;
+
+ mutex_lock(>lock);
+ ret = readl_poll_sleep_timeout(priv->base + SR, val, val & SR_LOCKED,
+ 1, 100);
+ if (!ret) {
+ writel(CTRL_SEN | CTRL_SADDR | CTRL_LOAD, priv->base + CTRL);
+ writel(CTRL_SADDR, priv->base + CTRL);
+
[PATCH 0/2] Add Xilinx clock wizard driver support
Hi, This series add support to enable clock wizard for zynq platform. Thanks, Zhengxun zhengxunli (2): clk: zynq: Add clock wizard driver board: Add Zynq Mxic picozed development board support arch/arm/dts/Makefile | 3 +- arch/arm/dts/zynq-mxic-picozed.dts | 66 ++ drivers/clk/Kconfig| 7 ++ drivers/clk/Makefile | 1 + drivers/clk/clk_wizard.c | 180 + 5 files changed, 256 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/zynq-mxic-picozed.dts create mode 100644 drivers/clk/clk_wizard.c -- 1.9.1
[PATCH 4/4] driver: spi: renesas_rpc_spi: Add mem_ops
This patch adds an implementation of exec_op, which support octal
mode and quad mode for reading flash and support existing single
mode for reading and writing flash concurrently.
Signed-off-by: zhengxunli
---
drivers/spi/renesas_rpc_spi.c | 144 ++
1 file changed, 144 insertions(+)
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index 1057651..ee8d49c 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include
#define RPC_CMNCR 0x /* R/W */
@@ -367,6 +368,144 @@ err:
return ret;
}
+static int rpc_spi_exec_mem_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ struct rpc_spi_priv *priv;
+ struct udevice *bus;
+ u32 wloop = (op->data.dir == SPI_MEM_DATA_OUT) ?
+DIV_ROUND_UP(op->data.nbytes, 4) : 0;
+ u32 smenr, smcr, cmncr;
+ u32 *datout;
+ int ret = 0;
+
+ bus = slave->dev->parent;
+ priv = dev_get_priv(bus);
+
+ if (op->cmd.buswidth == 2 || op->addr.buswidth == 2 ||
+ op->data.buswidth == 2 || op->addr.nbytes > 4)
+ return -ENOTSUPP;
+
+ smenr = 0;
+
+ if (op->data.dir == SPI_MEM_DATA_OUT ||
+ op->data.dir == SPI_MEM_NO_DATA) {
+ rpc_spi_claim_bus(slave->dev, true);
+
+ writel(0, priv->regs + RPC_SMCR);
+
+ /* Commnad(1) */
+ writel(RPC_SMCMR_CMD(op->cmd.opcode), priv->regs + RPC_SMCMR);
+
+ smenr |= RPC_SMENR_CDE;
+
+ smenr |= RPC_SMENR_CDB(fls(op->cmd.buswidth) - 1);
+
+ /* Address(3 or 4) */
+ if (op->addr.nbytes) {
+ writel(op->addr.val, priv->regs + RPC_SMADR);
+ if (op->addr.nbytes == 3)
+ smenr |= RPC_SMENR_ADE(0x7);
+ else
+ smenr |= RPC_SMENR_ADE(0xf);
+ smenr |= RPC_SMENR_ADB(fls(op->addr.buswidth) - 1);
+ } else {
+ writel(0, priv->regs + RPC_SMADR);
+ }
+
+ /* Dummy(0) */
+ writel(0, priv->regs + RPC_SMDMCR);
+
+ writel(0, priv->regs + RPC_SMOPR);
+
+ writel(0, priv->regs + RPC_SMDRENR);
+
+ /* Data(n) */
+ if (op->data.nbytes) {
+ datout = (u32 *)op->data.buf.out;
+
+ smenr |= RPC_SMENR_SPIDE(0xf);
+
+ smenr |= RPC_SMENR_SPIDB(fls(op->data.buswidth) - 1);
+
+ while (wloop--) {
+ smcr = RPC_SMCR_SPIWE | RPC_SMCR_SPIE;
+ if (wloop >= 1)
+ smcr |= RPC_SMCR_SSLKP;
+ writel(smenr, priv->regs + RPC_SMENR);
+ writel(*datout, priv->regs + RPC_SMWDR0);
+ writel(smcr, priv->regs + RPC_SMCR);
+ ret = rpc_spi_wait_tend(slave->dev);
+ if (ret)
+ goto err;
+ datout++;
+ smenr = RPC_SMENR_SPIDE(0xf);
+ }
+
+ ret = rpc_spi_wait_sslf(slave->dev);
+ } else {
+ writel(smenr, priv->regs + RPC_SMENR);
+ writel(RPC_SMCR_SPIE, priv->regs + RPC_SMCR);
+ ret = rpc_spi_wait_tend(slave->dev);
+ }
+ } else {/* Read data only, using DRx ext access */
+ rpc_spi_claim_bus(slave->dev, false);
+
+ if (op->cmd.buswidth > 4 || op->addr.buswidth > 4 ||
+ op->data.buswidth > 4) {
+ cmncr = readl(priv->regs + RPC_CMNCR);
+ cmncr |= RPC_CMNCR_BSZ(1);
+ writel(cmncr, priv->regs + RPC_CMNCR);
+ }
+
+ /* Command(1) */
+ writel(RPC_DRCMR_CMD(op->cmd.opcode), priv->regs + RPC_DRCMR);
+
+ smenr |= RPC_DRENR_CDE;
+
+ smenr |= RPC_DRENR_CDB(fls(op->cmd.buswidth) - 1);
+
+ /* Address(3 or 4) */
+ if (op->addr.nbytes) {
+ if (op->addr.nbytes == 3)
+ smenr |= RPC_DRENR_ADE(0x7);
+ else
+ smenr |= RPC_DRENR_ADE(0xf);
+ smenr |= RPC_DRENR_ADB(fls(op->addr.buswidth) - 1);
+ }
+
+ /* Dummy(n) */
+
[PATCH 3/4] arm: dts: r8a77995-u-boot: Add SPI Flash Support
Add U-Boot SPI Flash support for the Renesas Draak board and
configure RX and TX bus-width values to support octal I/O mode.
Signed-off-by: zhengxunli
---
arch/arm/dts/r8a77995-u-boot.dtsi | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/r8a77995-u-boot.dtsi
b/arch/arm/dts/r8a77995-u-boot.dtsi
index 0917a80..aa23af1 100644
--- a/arch/arm/dts/r8a77995-u-boot.dtsi
+++ b/arch/arm/dts/r8a77995-u-boot.dtsi
@@ -14,7 +14,16 @@
reg = <0 0xee20 0 0x100>, <0 0x0800 0 0>;
clocks = < CPG_MOD 917>;
bank-width = <2>;
- status = "disabled";
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <8>;
+ };
};
};
};
--
1.9.1
[PATCH 2/4] arm: dts: Add DT spi0 alias to Renesas Draak board
The spi0 alias is needed by the environment code to retrieve the SPI
flash. This patch provides the spi0 aliases, for Renesas Draak board.
Signed-off-by: zhengxunli
---
arch/arm/dts/r8a77995-draak.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/r8a77995-draak.dts b/arch/arm/dts/r8a77995-draak.dts
index 67634cb..cc2bc89 100644
--- a/arch/arm/dts/r8a77995-draak.dts
+++ b/arch/arm/dts/r8a77995-draak.dts
@@ -17,6 +17,7 @@
aliases {
serial0 =
ethernet0 =
+ spi0 =
};
backlight: backlight {
--
1.9.1
[PATCH 0/4] Add octal mode on Renesas Draak board
The MX66UW2G345G is Macronix flash with single and octal mode. Hence, for testing purposes, this patch adds SPI-MEM framework to support the octal mode on Renesas Draak board. The datasheet can be found in https://www.macronix.com/zh-tw/products/NOR-Flash/Pages/octaflash.aspx#1.8V. zhengxunli (4): mtd: spi-nor-ids: Add Macronix MX66UW2G345G arm: dts: Add DT spi0 alias to Renesas Draak board arm: dts: r8a77995-u-boot: Add SPI Flash Support driver: spi: renesas_rpc_spi: Add mem_ops arch/arm/dts/r8a77995-draak.dts | 1 + arch/arm/dts/r8a77995-u-boot.dtsi | 11 ++- drivers/mtd/spi/spi-nor-ids.c | 1 + drivers/spi/renesas_rpc_spi.c | 144 ++ 4 files changed, 156 insertions(+), 1 deletion(-) -- 1.9.1
[PATCH 1/4] mtd: spi-nor-ids: Add Macronix MX66UW2G345G
The MX66UW2G345G is Macronix Flash with SINGLE and OCTAL I/O. Hence,
add SPI_NOR_OCTAL_READ flag for this flash.
Signed-off-by: zhengxunli
---
drivers/mtd/spi/spi-nor-ids.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 5bd5dd3..4e8ab46 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -162,6 +162,7 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ |
SPI_NOR_4B_OPCODES | SECT_4K) },
{ INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) },
+ { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO/* STMICRO */
--
1.9.1
[PATCH 4/4] driver: spi: renesas_rpc_spi: Add mem_ops
From: zhengxun
This patch adds an implementation of exec_op, which support octal mode
and quad mode for reading flash and support existing single mode for
reading and writing flash concurrently.
Signed-off-by: zhengxun
---
drivers/spi/renesas_rpc_spi.c | 144 ++
1 file changed, 144 insertions(+)
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index d0ff918af8..4424cf0209 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include
#define RPC_CMNCR 0x /* R/W */
@@ -367,6 +368,144 @@ err:
return ret;
}
+static int rpc_spi_exec_mem_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ struct rpc_spi_priv *priv;
+ struct udevice *bus;
+ u32 wloop = (op->data.dir == SPI_MEM_DATA_OUT) ?
+DIV_ROUND_UP(op->data.nbytes, 4) : 0;
+ u32 smenr, smcr, cmncr;
+ u32 *datout;
+ int ret = 0;
+
+ bus = slave->dev->parent;
+ priv = dev_get_priv(bus);
+
+ if (op->cmd.buswidth == 2 || op->addr.buswidth == 2 ||
+ op->data.buswidth == 2 || op->addr.nbytes > 4)
+ return -ENOTSUPP;
+
+ smenr = 0;
+
+ if (op->data.dir == SPI_MEM_DATA_OUT ||
+ op->data.dir == SPI_MEM_NO_DATA) {
+ rpc_spi_claim_bus(slave->dev, true);
+
+ writel(0, priv->regs + RPC_SMCR);
+
+ /* Commnad(1) */
+ writel(RPC_SMCMR_CMD(op->cmd.opcode), priv->regs + RPC_SMCMR);
+
+ smenr |= RPC_SMENR_CDE;
+
+ smenr |= RPC_SMENR_CDB(fls(op->cmd.buswidth) - 1);
+
+ /* Address(3 or 4) */
+ if (op->addr.nbytes) {
+ writel(op->addr.val, priv->regs + RPC_SMADR);
+ if (op->addr.nbytes == 3)
+ smenr |= RPC_SMENR_ADE(0x7);
+ else
+ smenr |= RPC_SMENR_ADE(0xf);
+ smenr |= RPC_SMENR_ADB(fls(op->addr.buswidth) - 1);
+ } else {
+ writel(0, priv->regs + RPC_SMADR);
+ }
+
+ /* Dummy(0) */
+ writel(0, priv->regs + RPC_SMDMCR);
+
+ writel(0, priv->regs + RPC_SMOPR);
+
+ writel(0, priv->regs + RPC_SMDRENR);
+
+ /* Data(n) */
+ if (op->data.nbytes) {
+ datout = (u32 *)op->data.buf.out;
+
+ smenr |= RPC_SMENR_SPIDE(0xf);
+
+ smenr |= RPC_SMENR_SPIDB(fls(op->data.buswidth) - 1);
+
+ while (wloop--) {
+ smcr = RPC_SMCR_SPIWE | RPC_SMCR_SPIE;
+ if (wloop >= 1)
+ smcr |= RPC_SMCR_SSLKP;
+ writel(smenr, priv->regs + RPC_SMENR);
+ writel(*datout, priv->regs + RPC_SMWDR0);
+ writel(smcr, priv->regs + RPC_SMCR);
+ ret = rpc_spi_wait_tend(slave->dev);
+ if (ret)
+ goto err;
+ datout++;
+ smenr = RPC_SMENR_SPIDE(0xf);
+ }
+
+ ret = rpc_spi_wait_sslf(slave->dev);
+ } else {
+ writel(smenr, priv->regs + RPC_SMENR);
+ writel(RPC_SMCR_SPIE, priv->regs + RPC_SMCR);
+ ret = rpc_spi_wait_tend(slave->dev);
+ }
+ } else {/* Read data only, using DRx ext access */
+ rpc_spi_claim_bus(slave->dev, false);
+
+ if (op->cmd.buswidth > 4 || op->addr.buswidth > 4 ||
+ op->data.buswidth > 4) {
+ cmncr = readl(priv->regs + RPC_CMNCR);
+ cmncr |= RPC_CMNCR_BSZ(1);
+ writel(cmncr, priv->regs + RPC_CMNCR);
+ }
+
+ /* Command(1) */
+ writel(RPC_DRCMR_CMD(op->cmd.opcode), priv->regs + RPC_DRCMR);
+
+ smenr |= RPC_DRENR_CDE;
+
+ smenr |= RPC_DRENR_CDB(fls(op->cmd.buswidth) - 1);
+
+ /* Address(3 or 4) */
+ if (op->addr.nbytes) {
+ if (op->addr.nbytes == 3)
+ smenr |= RPC_DRENR_ADE(0x7);
+ else
+ smenr |= RPC_DRENR_ADE(0xf);
+ smenr |= RPC_DRENR_ADB(fls(op->addr.buswidth) - 1);
+ }
+
+ /* Dummy(n) */
+ if (op->dummy.nbytes) {
+ writel(op->dummy.nbytes, priv->regs + RPC_DRDMCR);
+ smenr |= RPC_DRENR_DME;
+
[PATCH 3/4] arm: dts: r8a77995-u-boot: Add SPI Flash Support
From: zhengxun
Add U-Boot SPI Flash support for the Renesas Draak board and configure
RX and TX bus-width values to support octal I/O mode.
Signed-off-by: zhengxun
---
arch/arm/dts/r8a77995-u-boot.dtsi | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/r8a77995-u-boot.dtsi
b/arch/arm/dts/r8a77995-u-boot.dtsi
index 8e9f6b7a7d..86aeeda474 100644
--- a/arch/arm/dts/r8a77995-u-boot.dtsi
+++ b/arch/arm/dts/r8a77995-u-boot.dtsi
@@ -14,7 +14,16 @@
reg = <0 0xee20 0 0x100>, <0 0x0800 0 0>;
clocks = < CPG_MOD 917>;
bank-width = <2>;
- status = "disabled";
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <8>;
+ };
};
};
};
--
2.17.1
[PATCH 2/4] arm: dts: Add DT spi0 alias to Renesas Draak board
From: zhengxun
The spi0 alias is needed by the environment code to retrieve the SPI
flash. This patch provides the spi0 aliases, for Renesas Draak board.
Signed-off-by: zhengxun
---
arch/arm/dts/r8a77995-draak.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/r8a77995-draak.dts b/arch/arm/dts/r8a77995-draak.dts
index 67634cb01d..cc2bc89216 100644
--- a/arch/arm/dts/r8a77995-draak.dts
+++ b/arch/arm/dts/r8a77995-draak.dts
@@ -17,6 +17,7 @@
aliases {
serial0 =
ethernet0 =
+ spi0 =
};
backlight: backlight {
--
2.17.1
[PATCH 1/4] mtd: spi-nor-ids: Add Macronix MX66UW2G345G
From: zhengxun
The MX66UW2G345G is Macronix Flash with SINGLE and OCTAL I/O. Hence,
add SPI_NOR_OCTAL_READ flag for this flash.
Signed-off-by: zhengxun
---
drivers/mtd/spi/spi-nor-ids.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index bc9d4f7e9f..5104b3ae57 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -162,6 +162,7 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ |
SPI_NOR_4B_OPCODES | SECT_4K) },
{ INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) },
+ { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO/* STMICRO */
--
2.17.1
[PATCH 0/4] Support Macronix MX66UW2G345G on Renesas Draak board
From: zhengxun The MX66UW2G345G is Macronix flash with single and octal mode. Hence, for testing purposes, this patch adds SPI-MEM framework to support the octal mode on Renesas Draak board. The datasheet can be found in https://www.macronix.com/zh-tw/products/NOR-Flash/Pages/octaflash.aspx#1.8V. zhengxun (4): mtd: spi-nor-ids: Add Macronix MX66UW2G345G arm: dts: Add DT spi0 alias to Renesas Draak board arm: dts: r8a77995-u-boot: Add SPI Flash Support driver: spi: renesas_rpc_spi: Add mem_ops arch/arm/dts/r8a77995-draak.dts | 1 + arch/arm/dts/r8a77995-u-boot.dtsi | 11 ++- drivers/mtd/spi/spi-nor-ids.c | 1 + drivers/spi/renesas_rpc_spi.c | 144 ++ 4 files changed, 156 insertions(+), 1 deletion(-) -- 2.17.1
