Re: [PATCH] ARM: zynq: DT: Enable all FCLKs by default
On 10/12/22 11:30, Michal Simek wrote: From: Christian Kohn The fclk-enable property is set to 0 which disables all FCLKs. Enable all FCLKs so they can be used as clock sources in the programmable logic. Signed-off-by: Christian Kohn Acked-by: Soren Brinkmann Signed-off-by: Michal Simek --- arch/arm/dts/zynq-7000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index edc147d63f1e..f72ef526f057 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -340,7 +340,7 @@ u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; - fclk-enable = <0>; + fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", Applied. M
[PATCH] ARM: zynq: DT: Enable all FCLKs by default
From: Christian Kohn The fclk-enable property is set to 0 which disables all FCLKs. Enable all FCLKs so they can be used as clock sources in the programmable logic. Signed-off-by: Christian Kohn Acked-by: Soren Brinkmann Signed-off-by: Michal Simek --- arch/arm/dts/zynq-7000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index edc147d63f1e..f72ef526f057 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -340,7 +340,7 @@ u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; - fclk-enable = <0>; + fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", -- 2.36.1
Re: [PATCH] ARM: zynq: DT: Enable all FCLKs by default
Hi Tom, On 7/7/22 14:31, Tom Rini wrote: On Thu, Jul 07, 2022 at 12:50:10PM +0200, Michal Simek wrote: From: Christian Kohn The fclk-enable property is set to 0 which disables all FCLKs. Enable all FCLKs so they can be used as clock sources in the programmable logic. Signed-off-by: Christian Kohn Signed-off-by: Michal Simek --- arch/arm/dts/zynq-7000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Since this (and the other patch today) are touching a common dtsi file, what is the status of these changes with upstream? Thanks. Versal reset DT header is in Linux kernel already mmio-sram is enabled for zc702 board in kernel already but it is generic for all. #stream-id-cells - already removed in the kernel And this fclk not sent to upstream linux yet. Thanks, Michal
Re: [PATCH] ARM: zynq: DT: Enable all FCLKs by default
On Thu, Jul 07, 2022 at 12:50:10PM +0200, Michal Simek wrote: > From: Christian Kohn > > The fclk-enable property is set to 0 which disables all FCLKs. > Enable all FCLKs so they can be used as clock sources in the > programmable logic. > > Signed-off-by: Christian Kohn > Signed-off-by: Michal Simek > --- > > arch/arm/dts/zynq-7000.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Since this (and the other patch today) are touching a common dtsi file, what is the status of these changes with upstream? Thanks. -- Tom signature.asc Description: PGP signature
[PATCH] ARM: zynq: DT: Enable all FCLKs by default
From: Christian Kohn The fclk-enable property is set to 0 which disables all FCLKs. Enable all FCLKs so they can be used as clock sources in the programmable logic. Signed-off-by: Christian Kohn Signed-off-by: Michal Simek --- arch/arm/dts/zynq-7000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 37155df0fd42..9626a0714625 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -329,7 +329,7 @@ u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; - fclk-enable = <0>; + fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", -- 2.36.1
