Re: [PATCH] riscv: Fix alignment of RELA sections in the linker scripts
Hi Rick, Bin,
On Tue, Jun 27, 2023 at 09:12:35AM +0800, Bin Meng wrote:
> On Tue, Jun 27, 2023 at 8:50 AM Rick Chen wrote:
> >
> > > From: Bin Meng
> > > Sent: Wednesday, June 21, 2023 11:07 PM
> > > To: u-boot@lists.denx.de
> > > Cc: Andrew Scull ; Leo Yu-Chi Liang(梁育齊)
> > > ; Rick Jian-Zhi Chen(陳建志) ;
> > > Simon Glass
> > > Subject: [PATCH] riscv: Fix alignment of RELA sections in the linker
> > > scripts
> > >
> > > In current linker script both .efi_runtime_rel and .rela.dyn sections are
> > > of RELA type whose entry size is either 12 (RV32) or 24 (RV64).
> > > These two are arranged as an continuous region on purpose so that the
> > > prelink-riscv executable can fix up the PIE addresses in one loop.
> > >
> > > However there is an 'ALIGN(8)' between these 2 sections which might cause
> > > a gap to be inserted between thesse 2 sections to satify the alignment
> > > requirement on RV32. This would break the assumption of the prelink
> > > process and generate an unbootable image.
> > >
> > > Fixes: 9a6569a043d3 ("riscv: Update alignment for some sections in linker
> > > scripts")
> > > Signed-off-by: Bin Meng
> > >
> > > ---
> > > This fix should go into the v2023.07 release.
> > >
> > > arch/riscv/cpu/u-boot.lds | 4 +---
> > > 1 file changed, 1 insertion(+), 3 deletions(-)
> >
> > Reviewed-by: Rick Chen
> >
> > Hi Leo,
> >
> > Please help to push this patch ASAP.
> >
>
> Thanks Rick. I will respin a v2 to fix the typos in the commit message.
>
> Regards,
> Bin
Thanks for the catch and the reminder.
The patch has been merged.
Best regards,
Leo
Re: [PATCH] riscv: Fix alignment of RELA sections in the linker scripts
On Tue, Jun 27, 2023 at 8:50 AM Rick Chen wrote:
>
> > From: Bin Meng
> > Sent: Wednesday, June 21, 2023 11:07 PM
> > To: u-boot@lists.denx.de
> > Cc: Andrew Scull ; Leo Yu-Chi Liang(梁育齊)
> > ; Rick Jian-Zhi Chen(陳建志) ;
> > Simon Glass
> > Subject: [PATCH] riscv: Fix alignment of RELA sections in the linker scripts
> >
> > In current linker script both .efi_runtime_rel and .rela.dyn sections are
> > of RELA type whose entry size is either 12 (RV32) or 24 (RV64).
> > These two are arranged as an continuous region on purpose so that the
> > prelink-riscv executable can fix up the PIE addresses in one loop.
> >
> > However there is an 'ALIGN(8)' between these 2 sections which might cause a
> > gap to be inserted between thesse 2 sections to satify the alignment
> > requirement on RV32. This would break the assumption of the prelink process
> > and generate an unbootable image.
> >
> > Fixes: 9a6569a043d3 ("riscv: Update alignment for some sections in linker
> > scripts")
> > Signed-off-by: Bin Meng
> >
> > ---
> > This fix should go into the v2023.07 release.
> >
> > arch/riscv/cpu/u-boot.lds | 4 +---
> > 1 file changed, 1 insertion(+), 3 deletions(-)
>
> Reviewed-by: Rick Chen
>
> Hi Leo,
>
> Please help to push this patch ASAP.
>
Thanks Rick. I will respin a v2 to fix the typos in the commit message.
Regards,
Bin
Re: [PATCH] riscv: Fix alignment of RELA sections in the linker scripts
> From: Bin Meng
> Sent: Wednesday, June 21, 2023 11:07 PM
> To: u-boot@lists.denx.de
> Cc: Andrew Scull ; Leo Yu-Chi Liang(梁育齊)
> ; Rick Jian-Zhi Chen(陳建志) ; Simon
> Glass
> Subject: [PATCH] riscv: Fix alignment of RELA sections in the linker scripts
>
> In current linker script both .efi_runtime_rel and .rela.dyn sections are of
> RELA type whose entry size is either 12 (RV32) or 24 (RV64).
> These two are arranged as an continuous region on purpose so that the
> prelink-riscv executable can fix up the PIE addresses in one loop.
>
> However there is an 'ALIGN(8)' between these 2 sections which might cause a
> gap to be inserted between thesse 2 sections to satify the alignment
> requirement on RV32. This would break the assumption of the prelink process
> and generate an unbootable image.
>
> Fixes: 9a6569a043d3 ("riscv: Update alignment for some sections in linker
> scripts")
> Signed-off-by: Bin Meng
>
> ---
> This fix should go into the v2023.07 release.
>
> arch/riscv/cpu/u-boot.lds | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Rick Chen
Hi Leo,
Please help to push this patch ASAP.
Thanks,
Rick
Re: [PATCH] riscv: Fix alignment of RELA sections in the linker scripts
On Wed, Jun 21, 2023 at 11:07 PM Bin Meng wrote:
>
> In current linker script both .efi_runtime_rel and .rela.dyn sections
> are of RELA type whose entry size is either 12 (RV32) or 24 (RV64).
> These two are arranged as an continuous region on purpose so that the
a continuous
> prelink-riscv executable can fix up the PIE addresses in one loop.
>
> However there is an 'ALIGN(8)' between these 2 sections which might
> cause a gap to be inserted between thesse 2 sections to satify the
typo: these, satisfy
> alignment requirement on RV32. This would break the assumption of
> the prelink process and generate an unbootable image.
>
> Fixes: 9a6569a043d3 ("riscv: Update alignment for some sections in linker
> scripts")
> Signed-off-by: Bin Meng
>
> ---
> This fix should go into the v2023.07 release.
>
Rick, ping?
[PATCH] riscv: Fix alignment of RELA sections in the linker scripts
In current linker script both .efi_runtime_rel and .rela.dyn sections
are of RELA type whose entry size is either 12 (RV32) or 24 (RV64).
These two are arranged as an continuous region on purpose so that the
prelink-riscv executable can fix up the PIE addresses in one loop.
However there is an 'ALIGN(8)' between these 2 sections which might
cause a gap to be inserted between thesse 2 sections to satify the
alignment requirement on RV32. This would break the assumption of
the prelink process and generate an unbootable image.
Fixes: 9a6569a043d3 ("riscv: Update alignment for some sections in linker
scripts")
Signed-off-by: Bin Meng
---
This fix should go into the v2023.07 release.
arch/riscv/cpu/u-boot.lds | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds
index 15b5cbc585..2ffe6ba3c8 100644
--- a/arch/riscv/cpu/u-boot.lds
+++ b/arch/riscv/cpu/u-boot.lds
@@ -48,7 +48,7 @@ SECTIONS
KEEP(*(SORT(__u_boot_list*)));
}
- . = ALIGN(4);
+ . = ALIGN(8);
.efi_runtime_rel : {
__efi_runtime_rel_start = .;
@@ -57,8 +57,6 @@ SECTIONS
__efi_runtime_rel_stop = .;
}
- . = ALIGN(8);
-
/DISCARD/ : { *(.rela.plt*) }
.rela.dyn : {
__rel_dyn_start = .;
--
2.25.1
