Re: [PATCH 02/11] arm: dts: Add Chameleonv3 handoff headers
On Mon, Apr 11, 2022 at 8:35 PM Simon Glass wrote: > > On Fri, 1 Apr 2022 at 06:44, Paweł Anikiel wrote: > > > > Add handoff headers for the Google Chameleonv3 variants: 480-2 and > > 270-3. Both files were generated using qts-filter-a10.sh. > > > > Signed-off-by: Paweł Anikiel > > --- > > .../dts/socfpga_chameleonv3_270_3_handoff.h | 305 ++ > > .../dts/socfpga_chameleonv3_480_2_handoff.h | 305 ++ > > 2 files changed, 610 insertions(+) > > create mode 100644 arch/arm/dts/socfpga_chameleonv3_270_3_handoff.h > > create mode 100644 arch/arm/dts/socfpga_chameleonv3_480_2_handoff.h > > If these are binding files needed for the dts, should they not go into > include/dt-bindings ? > > If not, can they go into arch/arm/include/asm/arch-... ? These files are generated by Quartus, they include things like pinmux configurations and clock settings. I put them in the same place as the existing arria10_socdk handoff: arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h I don't mind putting them in include/dt-bindings, but then we should probably also move the arria10_socdk one. What do you think? Regards, Paweł
Re: [PATCH 02/11] arm: dts: Add Chameleonv3 handoff headers
On Fri, 1 Apr 2022 at 06:44, Paweł Anikiel wrote: > > Add handoff headers for the Google Chameleonv3 variants: 480-2 and > 270-3. Both files were generated using qts-filter-a10.sh. > > Signed-off-by: Paweł Anikiel > --- > .../dts/socfpga_chameleonv3_270_3_handoff.h | 305 ++ > .../dts/socfpga_chameleonv3_480_2_handoff.h | 305 ++ > 2 files changed, 610 insertions(+) > create mode 100644 arch/arm/dts/socfpga_chameleonv3_270_3_handoff.h > create mode 100644 arch/arm/dts/socfpga_chameleonv3_480_2_handoff.h If these are binding files needed for the dts, should they not go into include/dt-bindings ? If not, can they go into arch/arm/include/asm/arch-... ? Regards, Simon
[PATCH 02/11] arm: dts: Add Chameleonv3 handoff headers
Add handoff headers for the Google Chameleonv3 variants: 480-2 and 270-3. Both files were generated using qts-filter-a10.sh. Signed-off-by: Paweł Anikiel --- .../dts/socfpga_chameleonv3_270_3_handoff.h | 305 ++ .../dts/socfpga_chameleonv3_480_2_handoff.h | 305 ++ 2 files changed, 610 insertions(+) create mode 100644 arch/arm/dts/socfpga_chameleonv3_270_3_handoff.h create mode 100644 arch/arm/dts/socfpga_chameleonv3_480_2_handoff.h diff --git a/arch/arm/dts/socfpga_chameleonv3_270_3_handoff.h b/arch/arm/dts/socfpga_chameleonv3_270_3_handoff.h new file mode 100644 index 00..9d8f4a0dd3 --- /dev/null +++ b/arch/arm/dts/socfpga_chameleonv3_270_3_handoff.h @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Intel Arria 10 SoCFPGA configuration + */ + +#ifndef __SOCFPGA_ARRIA10_CONFIG_H__ +#define __SOCFPGA_ARRIA10_CONFIG_H__ + +/* Clocks */ +#define CB_INTOSC_LS_CLK_HZ 6000 +#define EMAC0_CLK_HZ 25000 +#define EMAC1_CLK_HZ 25000 +#define EMAC2_CLK_HZ 25000 +#define EOSC1_CLK_HZ +#define F2H_FREE_CLK_HZ 2 +#define H2F_USER0_CLK_HZ 2 +#define H2F_USER1_CLK_HZ 1 +#define L3_MAIN_FREE_CLK_HZ 2 +#define SDMMC_CLK_HZ 2 +#define TPIU_CLK_HZ 1 +#define MAINPLLGRP_CNTR15CLK_CNT 900 +#define MAINPLLGRP_CNTR2CLK_CNT 900 +#define MAINPLLGRP_CNTR3CLK_CNT 900 +#define MAINPLLGRP_CNTR4CLK_CNT 900 +#define MAINPLLGRP_CNTR5CLK_CNT 900 +#define MAINPLLGRP_CNTR6CLK_CNT 7 +#define MAINPLLGRP_CNTR7CLK_CNT 7 +#define MAINPLLGRP_CNTR7CLK_SRC 0 +#define MAINPLLGRP_CNTR8CLK_CNT 15 +#define MAINPLLGRP_CNTR9CLK_CNT 900 +#define MAINPLLGRP_CNTR9CLK_SRC 0 +#define MAINPLLGRP_MPUCLK_CNT 0 +#define MAINPLLGRP_MPUCLK_SRC 0 +#define MAINPLLGRP_NOCCLK_CNT 0 +#define MAINPLLGRP_NOCCLK_SRC 0 +#define MAINPLLGRP_NOCDIV_CSATCLK 0 +#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1 +#define MAINPLLGRP_NOCDIV_CSTRACECLK 0 +#define MAINPLLGRP_NOCDIV_L4MAINCLK 0 +#define MAINPLLGRP_NOCDIV_L4MPCLK 1 +#define MAINPLLGRP_NOCDIV_L4SPCLK 2 +#define MAINPLLGRP_VCO0_PSRC 0 +#define MAINPLLGRP_VCO1_DENOM 32 +#define MAINPLLGRP_VCO1_NUMER 1584 +#define PERPLLGRP_CNTR2CLK_CNT 5 +#define PERPLLGRP_CNTR2CLK_SRC 1 +#define PERPLLGRP_CNTR3CLK_CNT 900 +#define PERPLLGRP_CNTR3CLK_SRC 1 +#define PERPLLGRP_CNTR4CLK_CNT 14 +#define PERPLLGRP_CNTR4CLK_SRC 1 +#define PERPLLGRP_CNTR5CLK_CNT 374 +#define PERPLLGRP_CNTR5CLK_SRC 1 +#define PERPLLGRP_CNTR6CLK_CNT 900 +#define PERPLLGRP_CNTR6CLK_SRC 0 +#define PERPLLGRP_CNTR7CLK_CNT 900 +#define PERPLLGRP_CNTR8CLK_CNT 900 +#define PERPLLGRP_CNTR8CLK_SRC 0 +#define PERPLLGRP_CNTR9CLK_CNT 900 +#define PERPLLGRP_EMACCTL_EMAC0SEL 0 +#define PERPLLGRP_EMACCTL_EMAC1SEL 0 +#define PERPLLGRP_EMACCTL_EMAC2SEL 0 +#define PERPLLGRP_GPIODIV_GPIODBCLK 32000 +#define PERPLLGRP_VCO0_PSRC 0 +#define PERPLLGRP_VCO1_DENOM 32 +#define PERPLLGRP_VCO1_NUMER 1485 +#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16 +#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8 +#define CLKMGR_TESTIOCTRL_PERICLKSEL 8 +#define ALTERAGRP_MPUCLK_MAINCNT 1 +#define ALTERAGRP_MPUCLK_PERICNT 900 +#define ALTERAGRP_NOCCLK_MAINCNT 7 +#define ALTERAGRP_NOCCLK_PERICNT 900 +#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \ + (ALTERAGRP_MPUCLK_MAINCNT)) +#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \ + (ALTERAGRP_NOCCLK_MAINCNT)) + +/* Pin Mux Configuration */ +#define CONFIG_IO_10_INPUT_BUF_EN 1 +#define CONFIG_IO_10_PD_DRV_STRG 10 +#define CONFIG_IO_10_PD_SLW_RT 1 +#define CONFIG_IO_10_PU_DRV_STRG 8 +#define CONFIG_IO_10_PU_SLW_RT 1 +#define CONFIG_IO_10_RTRIM 1 +#define CONFIG_IO_10_WK_PU_EN 0 +#define CONFIG_IO_11_INPUT_BUF_EN 1 +#define CONFIG_IO_11_PD_DRV_STRG 10 +#define CONFIG_IO_11_PD_SLW_RT 1 +#define CONFIG_IO_11_PU_DRV_STRG 8 +#define CONFIG_IO_11_PU_SLW_RT 1 +#define CONFIG_IO_11_RTRIM 1 +#define CONFIG_IO_11_WK_PU_EN 0 +#define CONFIG_IO_12_INPUT_BUF_EN 0 +#define CONFIG_IO_12_PD_DRV_STRG 0 +#define CONFIG_IO_12_PD_SLW_RT 0 +#define CONFIG_IO_12_PU_DRV_STRG 0 +#define CONFIG_IO_12_PU_SLW_RT 0 +#define CONFIG_IO_12_RTRIM 1 +#define CONFIG_IO_12_WK_PU_EN 1 +#define CONFIG_IO_13_INPUT_BUF_EN 0 +#define CONFIG_IO_13_PD_DRV_STRG 0 +#define CONFIG_IO_13_PD_SLW_RT 0 +#define CONFIG_IO_13_PU_DRV_STRG 0 +#define CONFIG_IO_13_PU_SLW_RT 0 +#define CONFIG_IO_13_RTRIM 1 +#define CONFIG_IO_13_WK_PU_EN 1 +#define CONFIG_IO_14_INPUT_BUF_EN 0 +#define CONFIG_IO_14_PD_DRV_STRG 0 +#define CONFIG_IO_14_PD_SLW_RT 0 +#define CONFIG_IO_14_PU_DRV_STRG 0 +#define CONFIG_IO_14_PU_SLW_RT 0 +#define CONFIG_IO_14_RTRIM 1 +#define CONFIG_IO_14_WK_PU_EN 1 +#define CONFIG_IO_15_INPUT_BUF_EN 0 +#define CONFIG_IO_15_PD_DRV_STRG 0 +#define CONFIG_IO_15_PD_SLW_RT 0 +#define CONFIG_IO_15_PU_DRV_STRG 0 +#define CONFIG_IO_15_PU_SLW_RT 0 +#define CONFIG_IO_15_RTRIM 1 +#define CONFIG_IO_15_WK_PU_EN 1 +#define CONFIG_IO_16_INPUT_BUF_EN 0 +#define CONFIG_IO_16_PD_DRV_STRG 10 +#define CONFIG_IO_16_PD_SLW_RT 1 +#define CONFIG_IO_16_PU_DRV_STRG 8 +#define
