From: Suman Anna
Introduce the basic AM62 SoC description dtsi files. While doing this,
lets reuse the DDR controller definition from AM64 as the instance is
the same
Signed-off-by: Gowtham Tammana
Signed-off-by: Suman Anna
Signed-off-by: Vignesh Raghavendra
---
arch/arm/dts/k3-am62-ddr.dtsi| 11 +
arch/arm/dts/k3-am62-main.dtsi | 503 +++
arch/arm/dts/k3-am62-mcu.dtsi| 36 +++
arch/arm/dts/k3-am62-wakeup.dtsi | 41 +++
arch/arm/dts/k3-am62.dtsi| 105 +++
arch/arm/dts/k3-am625.dtsi | 103 +++
6 files changed, 799 insertions(+)
create mode 100644 arch/arm/dts/k3-am62-ddr.dtsi
create mode 100644 arch/arm/dts/k3-am62-main.dtsi
create mode 100644 arch/arm/dts/k3-am62-mcu.dtsi
create mode 100644 arch/arm/dts/k3-am62-wakeup.dtsi
create mode 100644 arch/arm/dts/k3-am62.dtsi
create mode 100644 arch/arm/dts/k3-am625.dtsi
diff --git a/arch/arm/dts/k3-am62-ddr.dtsi b/arch/arm/dts/k3-am62-ddr.dtsi
new file mode 100644
index 00..0a8ced8f38
--- /dev/null
+++ b/arch/arm/dts/k3-am62-ddr.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-am64-ddr.dtsi"
+&memorycontroller {
+ power-domains = <&k3_pds 170 TI_SCI_PD_SHARED>,
+ <&k3_pds 55 TI_SCI_PD_SHARED>;
+ clocks = <&k3_clks 170 0>, <&k3_clks 16 4>;
+};
diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi
new file mode 100644
index 00..8516393d1e
--- /dev/null
+++ b/arch/arm/dts/k3-am62-main.dtsi
@@ -0,0 +1,503 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM625 SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+ oc_sram: sram@7000 {
+ compatible = "mmio-sram";
+ reg = <0x00 0x7000 0x00 0x1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x7000 0x1>;
+ };
+
+ gic500: interrupt-controller@180 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00 0x0180 0x00 0x1>, /* GICD */
+ <0x00 0x0188 0x00 0xc>, /* GICR */
+ <0x00 0x0188 0x00 0xc>, /* GICR */
+ <0x01 0x 0x00 0x2000>,/* GICC */
+ <0x01 0x0001 0x00 0x1000>,/* GICH */
+ <0x01 0x0002 0x00 0x2000>;/* GICV */
+ /*
+* vcpumntirq:
+* virtual CPU interface maintenance interrupt
+*/
+ interrupts = ;
+
+ gic_its: msi-controller@182 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x00 0x0182 0x00 0x1>;
+ socionext,synquacer-pre-its = <0x100 0x40>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ main_conf: syscon@10 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x00 0x0010 0x00 0x2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x0010 0x2>;
+
+ phy_gmii_sel: phy@4044 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4044 0x8>;
+ #phy-cells = <1>;
+ };
+ };
+
+ dmss: bus@4800 {
+ compatible = "simple-mfd";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges;
+ ranges = <0x00 0x4800 0x00 0x4800 0x00 0x0640>;
+
+ ti,sci-dev-id = <25>;
+
+ secure_proxy_main: mailbox@4d00 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x4d00 0x00 0x8>,
+ <0x00 0x4a60 0x00 0x8>,
+ <0x00 0x4a40 0x00 0x8>;
+ interrupt-names = "rx_012";
+ interrupts = ;
+ };
+
+ inta_main_dmss: interrupt-controller@4800 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x4800 0x00 0x10>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ msi-controller;
+
