[PATCH 1/5] clk: imx: add i.IMXRT1020 clk driver

[sbabic]

> Add i.MXRT1020 clk driver support.
> Signed-off-by: Giulio Benetti 
> Reviewed-by: Lukasz Majewski 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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Re: [PATCH 1/5] clk: imx: add i.IMXRT1020 clk driver

[Lukasz Majewski]

On Tue, 18 Feb 2020 20:02:51 +0100
Giulio Benetti  wrote:

> Add i.MXRT1020 clk driver support.
> 
> Signed-off-by: Giulio Benetti 
> ---
>  drivers/clk/imx/Kconfig |  16 ++
>  drivers/clk/imx/Makefile|   1 +
>  drivers/clk/imx/clk-imxrt1020.c | 227
>  include/dt-bindings/clock/imxrt1020-clock.h |
> 52 + 4 files changed, 296 insertions(+)
>  create mode 100644 drivers/clk/imx/clk-imxrt1020.c
>  create mode 100644 include/dt-bindings/clock/imxrt1020-clock.h
> 
> diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
> index 059bc2fbb9..96721bcbf3 100644
> --- a/drivers/clk/imx/Kconfig
> +++ b/drivers/clk/imx/Kconfig
> @@ -69,6 +69,22 @@ config CLK_IMX8MP
>   help
> This enables support clock driver for i.MX8MP platforms.
>  
> +config SPL_CLK_IMXRT1020
> + bool "SPL clock support for i.MXRT1020"
> + depends on ARCH_IMXRT && SPL
> + select SPL_CLK
> + select SPL_CLK_CCF
> + help
> +   This enables SPL DM/DTS support for clock driver in
> i.MXRT1020 +
> +config CLK_IMXRT1020
> + bool "Clock support for i.MXRT1020"
> + depends on ARCH_IMXRT
> + select CLK
> + select CLK_CCF
> + help
> +   This enables support clock driver for i.MXRT1020 platforms.
> +
>  config SPL_CLK_IMXRT1050
>   bool "SPL clock support for i.MXRT1050"
>   depends on ARCH_IMXRT && SPL
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index 1e8a49d0f3..01bbbdf3ae 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -17,4 +17,5 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o
> clk-pll14xx.o \ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o
> clk-pll14xx.o \ clk-composite-8m.o
>  
> +obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
>  obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
> diff --git a/drivers/clk/imx/clk-imxrt1020.c
> b/drivers/clk/imx/clk-imxrt1020.c new file mode 100644
> index 00..840f783940
> --- /dev/null
> +++ b/drivers/clk/imx/clk-imxrt1020.c
> @@ -0,0 +1,227 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright(C) 2020
> + * Author(s): Giulio Benetti 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "clk.h"
> +
> +static ulong imxrt1020_clk_get_rate(struct clk *clk)
> +{
> + struct clk *c;
> + int ret;
> +
> + debug("%s(#%lu)\n", __func__, clk->id);
> +
> + ret = clk_get_by_id(clk->id, );
> + if (ret)
> + return ret;
> +
> + return clk_get_rate(c);
> +}
> +
> +static ulong imxrt1020_clk_set_rate(struct clk *clk, unsigned long
> rate) +{
> + struct clk *c;
> + int ret;
> +
> + debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
> +
> + ret = clk_get_by_id(clk->id, );
> + if (ret)
> + return ret;
> +
> + return clk_set_rate(c, rate);
> +}
> +
> +static int __imxrt1020_clk_enable(struct clk *clk, bool enable)
> +{
> + struct clk *c;
> + int ret;
> +
> + debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
> +
> + ret = clk_get_by_id(clk->id, );
> + if (ret)
> + return ret;
> +
> + if (enable)
> + ret = clk_enable(c);
> + else
> + ret = clk_disable(c);
> +
> + return ret;
> +}
> +
> +static int imxrt1020_clk_disable(struct clk *clk)
> +{
> + return __imxrt1020_clk_enable(clk, 0);
> +}
> +
> +static int imxrt1020_clk_enable(struct clk *clk)
> +{
> + return __imxrt1020_clk_enable(clk, 1);
> +}
> +
> +static struct clk_ops imxrt1020_clk_ops = {
> + .set_rate = imxrt1020_clk_set_rate,
> + .get_rate = imxrt1020_clk_get_rate,
> + .enable = imxrt1020_clk_enable,
> + .disable = imxrt1020_clk_disable,
> +};
> +
> +static const char * const pll2_bypass_sels[] = {"pll2_sys", "osc", };
> +static const char * const pll3_bypass_sels[] = {"pll3_usb_otg",
> "osc", }; +
> +static const char *const pre_periph_sels[] = { "pll2_sys",
> "pll2_pfd3_297m", "pll3_pfd3_454_74m", "arm_podf", }; +static const
> char *const periph_sels[] = { "pre_periph_sel", "todo", }; +static
> const char *const usdhc_sels[] = { "pll2_pfd2_396m",
> "pll2_pfd0_352m", }; +static const char *const lpuart_sels[] = {
> "pll3_80m", "osc", }; +static const char *const semc_alt_sels[] = {
> "pll2_pfd2_396m", "pll3_pfd1_664_62m", }; +static const char *const
> semc_sels[] = { "periph_sel", "semc_alt_sel", }; + +static int
> imxrt1020_clk_probe(struct udevice *dev) +{
> + void *base;
> +
> + /* Anatop clocks */
> + base = (void *)ANATOP_BASE_ADDR;
> +
> + clk_dm(IMXRT1020_CLK_PLL2_SYS,
> +imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
> +  base + 0x30, 0x1));
> + clk_dm(IMXRT1020_CLK_PLL3_USB_OTG,
> +imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
> +  base + 0x10, 0x1));
> +
> + /* PLL bypass out 

[PATCH 1/5] clk: imx: add i.IMXRT1020 clk driver

[Giulio Benetti]

Add i.MXRT1020 clk driver support.

Signed-off-by: Giulio Benetti 
---
 drivers/clk/imx/Kconfig |  16 ++
 drivers/clk/imx/Makefile|   1 +
 drivers/clk/imx/clk-imxrt1020.c | 227 
 include/dt-bindings/clock/imxrt1020-clock.h |  52 +
 4 files changed, 296 insertions(+)
 create mode 100644 drivers/clk/imx/clk-imxrt1020.c
 create mode 100644 include/dt-bindings/clock/imxrt1020-clock.h

diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 059bc2fbb9..96721bcbf3 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -69,6 +69,22 @@ config CLK_IMX8MP
help
  This enables support clock driver for i.MX8MP platforms.
 
+config SPL_CLK_IMXRT1020
+   bool "SPL clock support for i.MXRT1020"
+   depends on ARCH_IMXRT && SPL
+   select SPL_CLK
+   select SPL_CLK_CCF
+   help
+ This enables SPL DM/DTS support for clock driver in i.MXRT1020
+
+config CLK_IMXRT1020
+   bool "Clock support for i.MXRT1020"
+   depends on ARCH_IMXRT
+   select CLK
+   select CLK_CCF
+   help
+ This enables support clock driver for i.MXRT1020 platforms.
+
 config SPL_CLK_IMXRT1050
bool "SPL clock support for i.MXRT1050"
depends on ARCH_IMXRT && SPL
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 1e8a49d0f3..01bbbdf3ae 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -17,4 +17,5 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o 
clk-pll14xx.o \
 obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
clk-composite-8m.o
 
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
 obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c
new file mode 100644
index 00..840f783940
--- /dev/null
+++ b/drivers/clk/imx/clk-imxrt1020.c
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright(C) 2020
+ * Author(s): Giulio Benetti 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk.h"
+
+static ulong imxrt1020_clk_get_rate(struct clk *clk)
+{
+   struct clk *c;
+   int ret;
+
+   debug("%s(#%lu)\n", __func__, clk->id);
+
+   ret = clk_get_by_id(clk->id, );
+   if (ret)
+   return ret;
+
+   return clk_get_rate(c);
+}
+
+static ulong imxrt1020_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+   struct clk *c;
+   int ret;
+
+   debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+   ret = clk_get_by_id(clk->id, );
+   if (ret)
+   return ret;
+
+   return clk_set_rate(c, rate);
+}
+
+static int __imxrt1020_clk_enable(struct clk *clk, bool enable)
+{
+   struct clk *c;
+   int ret;
+
+   debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+   ret = clk_get_by_id(clk->id, );
+   if (ret)
+   return ret;
+
+   if (enable)
+   ret = clk_enable(c);
+   else
+   ret = clk_disable(c);
+
+   return ret;
+}
+
+static int imxrt1020_clk_disable(struct clk *clk)
+{
+   return __imxrt1020_clk_enable(clk, 0);
+}
+
+static int imxrt1020_clk_enable(struct clk *clk)
+{
+   return __imxrt1020_clk_enable(clk, 1);
+}
+
+static struct clk_ops imxrt1020_clk_ops = {
+   .set_rate = imxrt1020_clk_set_rate,
+   .get_rate = imxrt1020_clk_get_rate,
+   .enable = imxrt1020_clk_enable,
+   .disable = imxrt1020_clk_disable,
+};
+
+static const char * const pll2_bypass_sels[] = {"pll2_sys", "osc", };
+static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "osc", };
+
+static const char *const pre_periph_sels[] = { "pll2_sys", "pll2_pfd3_297m", 
"pll3_pfd3_454_74m", "arm_podf", };
+static const char *const periph_sels[] = { "pre_periph_sel", "todo", };
+static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", 
};
+static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
+static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", 
"pll3_pfd1_664_62m", };
+static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
+
+static int imxrt1020_clk_probe(struct udevice *dev)
+{
+   void *base;
+
+   /* Anatop clocks */
+   base = (void *)ANATOP_BASE_ADDR;
+
+   clk_dm(IMXRT1020_CLK_PLL2_SYS,
+  imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
+base + 0x30, 0x1));
+   clk_dm(IMXRT1020_CLK_PLL3_USB_OTG,
+  imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
+base + 0x10, 0x1));
+
+   /* PLL bypass out */
+   clk_dm(IMXRT1020_CLK_PLL2_BYPASS,
+  imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
+pll2_bypass_sels,
+