Re: [PATCH 15/19] ARM: dts: renesas: Synchronize RZ R8A774A1 RZ/G2M DTs with Linux 6.5.3

2023-09-29 Thread Adam Ford 
On Sun, Sep 17, 2023 at 9:18 AM Marek Vasut
 wrote:
>
> Synchronize RZ R8A774A1 RZ/G2M DTs with Linux 6.5.3,
Thanks!

> commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
>
> Signed-off-by: Marek Vasut 

Reviewed-by: Adam Ford 

> ---
>  arch/arm/dts/beacon-renesom-baseboard.dtsi | 45 ++
>  arch/arm/dts/beacon-renesom-som.dtsi   |  2 +-
>  arch/arm/dts/hihope-common.dtsi| 21 --
>  arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts | 21 --
>  arch/arm/dts/r8a774a1-u-boot.dtsi  |  1 -
>  arch/arm/dts/r8a774a1.dtsi | 14 ---
>  6 files changed, 57 insertions(+), 47 deletions(-)
>
> diff --git a/arch/arm/dts/beacon-renesom-baseboard.dtsi 
> b/arch/arm/dts/beacon-renesom-baseboard.dtsi
> index 8166e3c1ff4..2e9927b9773 100644
> --- a/arch/arm/dts/beacon-renesom-baseboard.dtsi
> +++ b/arch/arm/dts/beacon-renesom-baseboard.dtsi
> @@ -367,7 +367,7 @@
>
> assigned-clocks = <&versaclock6_bb 1>, <&versaclock6_bb 2>,
>   <&versaclock6_bb 3>, <&versaclock6_bb 4>;
> -   assigned-clock-rates = <2400>, <2400>, <2400>,
> +   assigned-clock-rates = <2400>, <2400>, <24576000>,
><24576000>;
>
> OUT1 {
> @@ -437,20 +437,6 @@
> };
> };
>
> -   /* 0 - lcd_reset */
> -   /* 1 - lcd_pwr */
> -   /* 2 - lcd_select */
> -   /* 3 - backlight-enable */
> -   /* 4 - Touch_shdwn */
> -   /* 5 - LCD_H_pol */
> -   /* 6 - lcd_V_pol */
> -   gpio_exp1: gpio@20 {
> -   compatible = "onnn,pca9654";
> -   reg = <0x20>;
> -   gpio-controller;
> -   #gpio-cells = <2>;
> -   };
> -
> touchscreen@26 {
> compatible = "ilitek,ili2117";
> reg = <0x26>;
> @@ -482,6 +468,16 @@
> };
> };
> };
> +
> +   gpio_exp1: gpio@70 {
> +   compatible = "nxp,pca9538";
> +   reg = <0x70>;
> +   gpio-controller;
> +   #gpio-cells = <2>;
> +   gpio-line-names = "lcd_reset", "lcd_pwr", "lcd_select",
> + "backlight-enable", "Touch_shdwn",
> + "LCD_H_pol", "lcd_V_pol";
> +   };
>  };
>
>  &lvds0 {
> @@ -638,6 +634,25 @@
> #clock-cells = <1>;
> clock-frequency = <11289600>;
>
> +   /* Reference versaclock instead of audio_clk_a */
> +   clocks = <&cpg CPG_MOD 1005>,
> +<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
> +<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
> +<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
> +<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
> +<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
> +<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
> +<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
> +<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
> +<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
> +<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
> +<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
> +<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
> +<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
> +<&versaclock6_bb 4>, <&audio_clk_b>,
> +<&audio_clk_c>,
> +<&cpg CPG_CORE CPG_AUDIO_CLK_I>;
> +
> status = "okay";
>
> ports {
> diff --git a/arch/arm/dts/beacon-renesom-som.dtsi 
> b/arch/arm/dts/beacon-renesom-som.dtsi
> index d3fc8ffd5b4..68b04e56ae5 100644
> --- a/arch/arm/dts/beacon-renesom-som.dtsi
> +++ b/arch/arm/dts/beacon-renesom-som.dtsi
> @@ -59,7 +59,7 @@
> status = "okay";
>
> phy0: ethernet-phy@0 {
> -   compatible = "ethernet-phy-id004d.d074",
> +   compatible = "ethernet-phy-id0022.1640",
>  "ethernet-phy-ieee802.3-c22";
> reg = <0>;
> interrupt-parent = <&gpio2>;
> diff --git a/arch/arm/dts/hihope-common.dtsi b/arch/arm/dts/hihope-common.dtsi
> index b1eb6a08029..83104af2813 100644
> --- a/arch/arm/dts/hihope-common.dtsi
> +++ b/arch/arm/dts/hihope-common.dtsi
> @@ -3,15 +3,26 @@
>   * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
>   * HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts
>   *
> - * Copyright (C) 2021 Renesas Electronics Corp.
> + * Copyright (C) 2019 Renesas Electronics Corp.
>   */
>
>  #include 
>
>  / {
> aliases {
> +   i2c0 = &i2c0;
> +   i2c1 = &i2c1;
> +   i2c2 = &i2c2;
> +   i2c3 = &i2c3;
> +   i2c4 = &i2c4;
> +   i2c5 = &i2c5;
> +   i2c6 = &i2c6;
> +   i2c7 = &iic_pmic;
> serial0 = &scif2;
> serial1 = &hscif0;
> +

[PATCH 15/19] ARM: dts: renesas: Synchronize RZ R8A774A1 RZ/G2M DTs with Linux 6.5.3

2023-09-17 Thread Marek Vasut 
Synchronize RZ R8A774A1 RZ/G2M DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut 
---
 arch/arm/dts/beacon-renesom-baseboard.dtsi | 45 ++
 arch/arm/dts/beacon-renesom-som.dtsi   |  2 +-
 arch/arm/dts/hihope-common.dtsi| 21 --
 arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts | 21 --
 arch/arm/dts/r8a774a1-u-boot.dtsi  |  1 -
 arch/arm/dts/r8a774a1.dtsi | 14 ---
 6 files changed, 57 insertions(+), 47 deletions(-)

diff --git a/arch/arm/dts/beacon-renesom-baseboard.dtsi 
b/arch/arm/dts/beacon-renesom-baseboard.dtsi
index 8166e3c1ff4..2e9927b9773 100644
--- a/arch/arm/dts/beacon-renesom-baseboard.dtsi
+++ b/arch/arm/dts/beacon-renesom-baseboard.dtsi
@@ -367,7 +367,7 @@
 
assigned-clocks = <&versaclock6_bb 1>, <&versaclock6_bb 2>,
  <&versaclock6_bb 3>, <&versaclock6_bb 4>;
-   assigned-clock-rates = <2400>, <2400>, <2400>,
+   assigned-clock-rates = <2400>, <2400>, <24576000>,
   <24576000>;
 
OUT1 {
@@ -437,20 +437,6 @@
};
};
 
-   /* 0 - lcd_reset */
-   /* 1 - lcd_pwr */
-   /* 2 - lcd_select */
-   /* 3 - backlight-enable */
-   /* 4 - Touch_shdwn */
-   /* 5 - LCD_H_pol */
-   /* 6 - lcd_V_pol */
-   gpio_exp1: gpio@20 {
-   compatible = "onnn,pca9654";
-   reg = <0x20>;
-   gpio-controller;
-   #gpio-cells = <2>;
-   };
-
touchscreen@26 {
compatible = "ilitek,ili2117";
reg = <0x26>;
@@ -482,6 +468,16 @@
};
};
};
+
+   gpio_exp1: gpio@70 {
+   compatible = "nxp,pca9538";
+   reg = <0x70>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   gpio-line-names = "lcd_reset", "lcd_pwr", "lcd_select",
+ "backlight-enable", "Touch_shdwn",
+ "LCD_H_pol", "lcd_V_pol";
+   };
 };
 
 &lvds0 {
@@ -638,6 +634,25 @@
#clock-cells = <1>;
clock-frequency = <11289600>;
 
+   /* Reference versaclock instead of audio_clk_a */
+   clocks = <&cpg CPG_MOD 1005>,
+<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+<&versaclock6_bb 4>, <&audio_clk_b>,
+<&audio_clk_c>,
+<&cpg CPG_CORE CPG_AUDIO_CLK_I>;
+
status = "okay";
 
ports {
diff --git a/arch/arm/dts/beacon-renesom-som.dtsi 
b/arch/arm/dts/beacon-renesom-som.dtsi
index d3fc8ffd5b4..68b04e56ae5 100644
--- a/arch/arm/dts/beacon-renesom-som.dtsi
+++ b/arch/arm/dts/beacon-renesom-som.dtsi
@@ -59,7 +59,7 @@
status = "okay";
 
phy0: ethernet-phy@0 {
-   compatible = "ethernet-phy-id004d.d074",
+   compatible = "ethernet-phy-id0022.1640",
 "ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupt-parent = <&gpio2>;
diff --git a/arch/arm/dts/hihope-common.dtsi b/arch/arm/dts/hihope-common.dtsi
index b1eb6a08029..83104af2813 100644
--- a/arch/arm/dts/hihope-common.dtsi
+++ b/arch/arm/dts/hihope-common.dtsi
@@ -3,15 +3,26 @@
  * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
  * HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts
  *
- * Copyright (C) 2021 Renesas Electronics Corp.
+ * Copyright (C) 2019 Renesas Electronics Corp.
  */
 
 #include 
 
 / {
aliases {
+   i2c0 = &i2c0;
+   i2c1 = &i2c1;
+   i2c2 = &i2c2;
+   i2c3 = &i2c3;
+   i2c4 = &i2c4;
+   i2c5 = &i2c5;
+   i2c6 = &i2c6;
+   i2c7 = &iic_pmic;
serial0 = &scif2;
serial1 = &hscif0;
+   mmc0 = &sdhi3;
+   mmc1 = &sdhi0;
+   mmc2 = &sdhi2;
};
 
chosen {
@@ -50,7 +61,7 @@
};
};
 
-   reg_1p8v: regulator0 {
+   reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";