Re: [PATCH 2/3] net: xilinx: axi_mrmac: Add MRMAC driver
Hi Ramon, On 6/28/21 7:10 PM, Ramon Fried wrote: > On Mon, Jun 28, 2021 at 9:37 AM Michal Simek wrote: >> >> Hi Ramon, >> we have been internally talking about splitting DMA handling out of >> driver. It is also about taking out axi dma out of axi emac driver. I >> have already asked Ashok to take a look at it but I expect it is not >> that straightforward process as it could be. That's why I asked Ashok to >> send this initial version to get at least one configuration going and >> start to look at u-boot dma framework to be able to get axi dma out of >> axi emac and mcdma out of mrmac driver. >> Then we should be able to use mcdma with axi email and axi dma with mrmac. >> Would be wonderful if you can test this configuraiton on your HW with >> mcdma wired and definitely would be great to cooperate on dma separation >> via u-boot dma framework. >> >> Thanks, >> Michal >> >> > Hi Michal, > I have a working driver supporting MRMAC 25Gb/100Gb using the AXI emac driver. Can you also send it out as RFC to be around? > I would love to see the DMA taken out of the driver, or supporting > both options inside the driver. We need to go that direction for sure. It just simply takes some time to get there. We have never used dma framework on any Xilinx devices that's why we need to learn how to use it and what it is missing. > I will gladly help you test on our HW (VCK5000) with our specific > configuration. Wonderful. Thanks, Michal
Re: [PATCH 2/3] net: xilinx: axi_mrmac: Add MRMAC driver
On Mon, Jun 28, 2021 at 9:37 AM Michal Simek wrote: > > Hi Ramon, > we have been internally talking about splitting DMA handling out of > driver. It is also about taking out axi dma out of axi emac driver. I > have already asked Ashok to take a look at it but I expect it is not > that straightforward process as it could be. That's why I asked Ashok to > send this initial version to get at least one configuration going and > start to look at u-boot dma framework to be able to get axi dma out of > axi emac and mcdma out of mrmac driver. > Then we should be able to use mcdma with axi email and axi dma with mrmac. > Would be wonderful if you can test this configuraiton on your HW with > mcdma wired and definitely would be great to cooperate on dma separation > via u-boot dma framework. > > Thanks, > Michal > > Hi Michal, I have a working driver supporting MRMAC 25Gb/100Gb using the AXI emac driver. I would love to see the DMA taken out of the driver, or supporting both options inside the driver. I will gladly help you test on our HW (VCK5000) with our specific configuration. Thanks, Ramon
RE: [PATCH 2/3] net: xilinx: axi_mrmac: Add MRMAC driver
Hi Simon, Thanks for the review. I will address the review points and send V2. Thanks, Ashok > -Original Message- > From: Simon Glass > Sent: Sunday, June 27, 2021 12:02 AM > To: Ashok Reddy Soma > Cc: U-Boot Mailing List ; Joe Hershberger > ; Ramon Fried ; Michal > Simek ; git ; Heinrich Schuchardt > ; Robert Marko ; Alex > Nemirovsky ; Sean Anderson > ; Weijie Gao ; Rayagonda > Kokatanur ; Stefan Bosch > ; Anastasiia Lukianenko > ; somaashokre...@gmail.com > Subject: Re: [PATCH 2/3] net: xilinx: axi_mrmac: Add MRMAC driver > > Hi Ashok, > > On Thu, 24 Jun 2021 at 00:43, Ashok Reddy Soma > wrote: > > > > Add support for xilinx multirate(MRMAC) ethernet driver. > > This driver uses multichannel DMA(MCDMA) for data transfers of MRMAC. > > Added support for 4 ports of MRMAC for speeds 10G and 25G. > > MCDMA supports upto 16 channels but in this driver we have setup only > > one channel which is enough. > > > > Tested 10G and 25G on all 4 ports. > > > > Signed-off-by: Ashok Reddy Soma > > --- > > > > MAINTAINERS| 1 + > > drivers/net/Kconfig| 9 + > > drivers/net/Makefile | 1 + > > drivers/net/xilinx_axi_mrmac.c | 525 > > + drivers/net/xilinx_axi_mrmac.h | > > 192 > > 5 files changed, 728 insertions(+) > > create mode 100644 drivers/net/xilinx_axi_mrmac.c create mode 100644 > > drivers/net/xilinx_axi_mrmac.h > > > > diff --git a/MAINTAINERS b/MAINTAINERS index 2accd1fb83..cc05e13968 > > 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -543,6 +543,7 @@ M: Michal Simek > > S: Maintained > > T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git > > F: arch/arm/mach-versal/ > > +F: drivers/net/xilinx_axi_mrmac.* > > F: drivers/watchdog/xilinx_wwdt.c > > N: (? > > > diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index > > 9fc28b149d..ccc5fc8fb6 100644 > > --- a/drivers/net/Kconfig > > +++ b/drivers/net/Kconfig > > @@ -617,6 +617,15 @@ config XILINX_AXIEMAC > > help > > This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. > > > > +config XILINX_AXIMRMAC > > + depends on DM_ETH && ARCH_VERSAL > > + bool "Xilinx AXI MRMAC" > > + help > > + MRMAC is a high performance, low latency, adaptable Ethernet > > + integrated hard IP. This can be configured up to four ports with > > MAC > > + rates from 10GE to 100GE. This could be present in some of the > > Xilinx > > + Versal designs. > > + > > config XILINX_EMACLITE > > depends on DM_ETH > > select PHYLIB > > diff --git a/drivers/net/Makefile b/drivers/net/Makefile index > > d56baa65b2..77a1d23dd3 100644 > > --- a/drivers/net/Makefile > > +++ b/drivers/net/Makefile > > @@ -78,6 +78,7 @@ obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o > > obj-$(CONFIG_ULI526X) += uli526x.o > > obj-$(CONFIG_VSC7385_ENET) += vsc7385.o > > obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o > > +obj-$(CONFIG_XILINX_AXIMRMAC) += xilinx_axi_mrmac.o > > obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o > > obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o > > obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/ > > diff --git a/drivers/net/xilinx_axi_mrmac.c > > b/drivers/net/xilinx_axi_mrmac.c new file mode 100644 index > > 00..bffedf8280 > > --- /dev/null > > +++ b/drivers/net/xilinx_axi_mrmac.c > > @@ -0,0 +1,525 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Xilinx Multirate Ethernet MAC(MRMAC) driver > > + * > > + * Author(s): Ashok Reddy Soma > > + * Michal Simek > > + * > > + * Copyright (C) 2021 Xilinx, Inc. All rights reserved. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include "xilinx_axi_mrmac.h" > > + > > +static u8 rxframe[RX_DESC * PKTSIZE_ALIGN] > > +__attribute((aligned(DMAALIGN))); static u8 txminframe[MIN_PKT_SIZE] > > +__attribute((aligned(DMAALIGN))); > > Please put this all in priv_auto > > > + > > +/* Static buffer descriptors: > > + * MRMAC needs atleast two buffer descriptors for the TX/RX to happen. > > + * Otherwise MRMAC wi
Re: [PATCH 2/3] net: xilinx: axi_mrmac: Add MRMAC driver
Hi Ramon,
On 6/27/21 9:56 PM, Ramon Fried wrote:
> On Sat, Jun 26, 2021 at 9:32 PM Simon Glass wrote:
>>
>> Hi Ashok,
>>
>> On Thu, 24 Jun 2021 at 00:43, Ashok Reddy Soma
>> wrote:
>>>
>>> Add support for xilinx multirate(MRMAC) ethernet driver.
>>> This driver uses multichannel DMA(MCDMA) for data transfers of MRMAC.
>>> Added support for 4 ports of MRMAC for speeds 10G and 25G.
>>> MCDMA supports upto 16 channels but in this driver we have setup only
>>> one channel which is enough.
>>>
>>> Tested 10G and 25G on all 4 ports.
>>>
>>> Signed-off-by: Ashok Reddy Soma
>>> ---
>>>
>>> MAINTAINERS| 1 +
>>> drivers/net/Kconfig| 9 +
>>> drivers/net/Makefile | 1 +
>>> drivers/net/xilinx_axi_mrmac.c | 525 +
>>> drivers/net/xilinx_axi_mrmac.h | 192
>>> 5 files changed, 728 insertions(+)
>>> create mode 100644 drivers/net/xilinx_axi_mrmac.c
>>> create mode 100644 drivers/net/xilinx_axi_mrmac.h
>>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index 2accd1fb83..cc05e13968 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -543,6 +543,7 @@ M: Michal Simek
>>> S: Maintained
>>> T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
>>> F: arch/arm/mach-versal/
>>> +F: drivers/net/xilinx_axi_mrmac.*
>>> F: drivers/watchdog/xilinx_wwdt.c
>>> N: (?>>
>>> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
>>> index 9fc28b149d..ccc5fc8fb6 100644
>>> --- a/drivers/net/Kconfig
>>> +++ b/drivers/net/Kconfig
>>> @@ -617,6 +617,15 @@ config XILINX_AXIEMAC
>>> help
>>> This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.
>>>
>>> +config XILINX_AXIMRMAC
>>> + depends on DM_ETH && ARCH_VERSAL
>>> + bool "Xilinx AXI MRMAC"
>>> + help
>>> + MRMAC is a high performance, low latency, adaptable Ethernet
>>> + integrated hard IP. This can be configured up to four ports with
>>> MAC
>>> + rates from 10GE to 100GE. This could be present in some of the
>>> Xilinx
>>> + Versal designs.
>>> +
>>> config XILINX_EMACLITE
>>> depends on DM_ETH
>>> select PHYLIB
>>> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
>>> index d56baa65b2..77a1d23dd3 100644
>>> --- a/drivers/net/Makefile
>>> +++ b/drivers/net/Makefile
>>> @@ -78,6 +78,7 @@ obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
>>> obj-$(CONFIG_ULI526X) += uli526x.o
>>> obj-$(CONFIG_VSC7385_ENET) += vsc7385.o
>>> obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
>>> +obj-$(CONFIG_XILINX_AXIMRMAC) += xilinx_axi_mrmac.o
>>> obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
>>> obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
>>> obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
>>> diff --git a/drivers/net/xilinx_axi_mrmac.c b/drivers/net/xilinx_axi_mrmac.c
>>> new file mode 100644
>>> index 00..bffedf8280
>>> --- /dev/null
>>> +++ b/drivers/net/xilinx_axi_mrmac.c
>>> @@ -0,0 +1,525 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Xilinx Multirate Ethernet MAC(MRMAC) driver
>>> + *
>>> + * Author(s): Ashok Reddy Soma
>>> + * Michal Simek
>>> + *
>>> + * Copyright (C) 2021 Xilinx, Inc. All rights reserved.
>>> + */
>>> +
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include "xilinx_axi_mrmac.h"
>>> +
>>> +static u8 rxframe[RX_DESC * PKTSIZE_ALIGN]
>>> __attribute((aligned(DMAALIGN)));
>>> +static u8 txminframe[MIN_PKT_SIZE] __attribute((aligned(DMAALIGN)));
>>
>> Please put this all in priv_auto
>>
>>> +
>>> +/* Static buffer descriptors:
>>> + * MRMAC needs atleast two buffer descriptors for the TX/RX to happen.
>>> + * Otherwise MRMAC will drop the packets. So, have two tx and rx bd's here.
>>> + */
>>> +static struct mcdma_bd tx_bd[TX_DESC] __attribute((aligned(DMAALIGN)));
>>> +static struct mcdma_bd rx_bd[RX_DESC] __attribute((aligned(DMAALIGN)));
>>
>> same here
>>
>>> +
>>> +static void axi_mrmac_dma_write(struct mcdma_bd *bd, u32 *desc)
>>> +{
>>> + if (IS_ENABLED(CONFIG_PHYS_64BIT))
>>> + writeq((unsigned long)bd, desc);
>>> + else
>>> + writel((uintptr_t)bd, desc);
>>> +}
>>> +
>>> +static int axi_mrmac_ethernet_init(struct axi_mrmac_priv *priv)
>>
>> function comment...what does it return?
>>
>>> +{
>>> + struct mrmac_regs *regs = priv->iobase;
>>> + u32 val, reg;
>>> + u32 ret;
>>> +
>>> + /* Perform all the RESET's required */
>>> + val = readl(>reset);
>>> + val |= MRMAC_RX_SERDES_RST_MASK | MRMAC_TX_SERDES_RST_MASK |
>>> + MRMAC_RX_RST_MASK | MRMAC_TX_RST_MASK;
>>> + writel(val, >reset);
>>
>> setbits_le32(>reset, ...)
>>
>> Take a look at the other similar functions which can help in this driver.
>>
>>> +
>>> + mdelay(MRMAC_RESET_DELAY);
>>> +
>>> + /* Configure Mode register
Re: [PATCH 2/3] net: xilinx: axi_mrmac: Add MRMAC driver
On Sat, Jun 26, 2021 at 9:32 PM Simon Glass wrote:
>
> Hi Ashok,
>
> On Thu, 24 Jun 2021 at 00:43, Ashok Reddy Soma
> wrote:
> >
> > Add support for xilinx multirate(MRMAC) ethernet driver.
> > This driver uses multichannel DMA(MCDMA) for data transfers of MRMAC.
> > Added support for 4 ports of MRMAC for speeds 10G and 25G.
> > MCDMA supports upto 16 channels but in this driver we have setup only
> > one channel which is enough.
> >
> > Tested 10G and 25G on all 4 ports.
> >
> > Signed-off-by: Ashok Reddy Soma
> > ---
> >
> > MAINTAINERS| 1 +
> > drivers/net/Kconfig| 9 +
> > drivers/net/Makefile | 1 +
> > drivers/net/xilinx_axi_mrmac.c | 525 +
> > drivers/net/xilinx_axi_mrmac.h | 192
> > 5 files changed, 728 insertions(+)
> > create mode 100644 drivers/net/xilinx_axi_mrmac.c
> > create mode 100644 drivers/net/xilinx_axi_mrmac.h
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 2accd1fb83..cc05e13968 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -543,6 +543,7 @@ M: Michal Simek
> > S: Maintained
> > T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
> > F: arch/arm/mach-versal/
> > +F: drivers/net/xilinx_axi_mrmac.*
> > F: drivers/watchdog/xilinx_wwdt.c
> > N: (? >
> > diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> > index 9fc28b149d..ccc5fc8fb6 100644
> > --- a/drivers/net/Kconfig
> > +++ b/drivers/net/Kconfig
> > @@ -617,6 +617,15 @@ config XILINX_AXIEMAC
> > help
> > This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.
> >
> > +config XILINX_AXIMRMAC
> > + depends on DM_ETH && ARCH_VERSAL
> > + bool "Xilinx AXI MRMAC"
> > + help
> > + MRMAC is a high performance, low latency, adaptable Ethernet
> > + integrated hard IP. This can be configured up to four ports with
> > MAC
> > + rates from 10GE to 100GE. This could be present in some of the
> > Xilinx
> > + Versal designs.
> > +
> > config XILINX_EMACLITE
> > depends on DM_ETH
> > select PHYLIB
> > diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> > index d56baa65b2..77a1d23dd3 100644
> > --- a/drivers/net/Makefile
> > +++ b/drivers/net/Makefile
> > @@ -78,6 +78,7 @@ obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
> > obj-$(CONFIG_ULI526X) += uli526x.o
> > obj-$(CONFIG_VSC7385_ENET) += vsc7385.o
> > obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
> > +obj-$(CONFIG_XILINX_AXIMRMAC) += xilinx_axi_mrmac.o
> > obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
> > obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
> > obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
> > diff --git a/drivers/net/xilinx_axi_mrmac.c b/drivers/net/xilinx_axi_mrmac.c
> > new file mode 100644
> > index 00..bffedf8280
> > --- /dev/null
> > +++ b/drivers/net/xilinx_axi_mrmac.c
> > @@ -0,0 +1,525 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Xilinx Multirate Ethernet MAC(MRMAC) driver
> > + *
> > + * Author(s): Ashok Reddy Soma
> > + * Michal Simek
> > + *
> > + * Copyright (C) 2021 Xilinx, Inc. All rights reserved.
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include "xilinx_axi_mrmac.h"
> > +
> > +static u8 rxframe[RX_DESC * PKTSIZE_ALIGN]
> > __attribute((aligned(DMAALIGN)));
> > +static u8 txminframe[MIN_PKT_SIZE] __attribute((aligned(DMAALIGN)));
>
> Please put this all in priv_auto
>
> > +
> > +/* Static buffer descriptors:
> > + * MRMAC needs atleast two buffer descriptors for the TX/RX to happen.
> > + * Otherwise MRMAC will drop the packets. So, have two tx and rx bd's here.
> > + */
> > +static struct mcdma_bd tx_bd[TX_DESC] __attribute((aligned(DMAALIGN)));
> > +static struct mcdma_bd rx_bd[RX_DESC] __attribute((aligned(DMAALIGN)));
>
> same here
>
> > +
> > +static void axi_mrmac_dma_write(struct mcdma_bd *bd, u32 *desc)
> > +{
> > + if (IS_ENABLED(CONFIG_PHYS_64BIT))
> > + writeq((unsigned long)bd, desc);
> > + else
> > + writel((uintptr_t)bd, desc);
> > +}
> > +
> > +static int axi_mrmac_ethernet_init(struct axi_mrmac_priv *priv)
>
> function comment...what does it return?
>
> > +{
> > + struct mrmac_regs *regs = priv->iobase;
> > + u32 val, reg;
> > + u32 ret;
> > +
> > + /* Perform all the RESET's required */
> > + val = readl(>reset);
> > + val |= MRMAC_RX_SERDES_RST_MASK | MRMAC_TX_SERDES_RST_MASK |
> > + MRMAC_RX_RST_MASK | MRMAC_TX_RST_MASK;
> > + writel(val, >reset);
>
> setbits_le32(>reset, ...)
>
> Take a look at the other similar functions which can help in this driver.
>
> > +
> > + mdelay(MRMAC_RESET_DELAY);
> > +
> > + /* Configure Mode register */
> > + reg = readl(>mode);
> > +
> > + debug("Configuring
Re: [PATCH 2/3] net: xilinx: axi_mrmac: Add MRMAC driver
Hi Ashok,
On Thu, 24 Jun 2021 at 00:43, Ashok Reddy Soma
wrote:
>
> Add support for xilinx multirate(MRMAC) ethernet driver.
> This driver uses multichannel DMA(MCDMA) for data transfers of MRMAC.
> Added support for 4 ports of MRMAC for speeds 10G and 25G.
> MCDMA supports upto 16 channels but in this driver we have setup only
> one channel which is enough.
>
> Tested 10G and 25G on all 4 ports.
>
> Signed-off-by: Ashok Reddy Soma
> ---
>
> MAINTAINERS| 1 +
> drivers/net/Kconfig| 9 +
> drivers/net/Makefile | 1 +
> drivers/net/xilinx_axi_mrmac.c | 525 +
> drivers/net/xilinx_axi_mrmac.h | 192
> 5 files changed, 728 insertions(+)
> create mode 100644 drivers/net/xilinx_axi_mrmac.c
> create mode 100644 drivers/net/xilinx_axi_mrmac.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 2accd1fb83..cc05e13968 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -543,6 +543,7 @@ M: Michal Simek
> S: Maintained
> T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
> F: arch/arm/mach-versal/
> +F: drivers/net/xilinx_axi_mrmac.*
> F: drivers/watchdog/xilinx_wwdt.c
> N: (?
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index 9fc28b149d..ccc5fc8fb6 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -617,6 +617,15 @@ config XILINX_AXIEMAC
> help
> This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.
>
> +config XILINX_AXIMRMAC
> + depends on DM_ETH && ARCH_VERSAL
> + bool "Xilinx AXI MRMAC"
> + help
> + MRMAC is a high performance, low latency, adaptable Ethernet
> + integrated hard IP. This can be configured up to four ports with MAC
> + rates from 10GE to 100GE. This could be present in some of the
> Xilinx
> + Versal designs.
> +
> config XILINX_EMACLITE
> depends on DM_ETH
> select PHYLIB
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index d56baa65b2..77a1d23dd3 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -78,6 +78,7 @@ obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
> obj-$(CONFIG_ULI526X) += uli526x.o
> obj-$(CONFIG_VSC7385_ENET) += vsc7385.o
> obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
> +obj-$(CONFIG_XILINX_AXIMRMAC) += xilinx_axi_mrmac.o
> obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
> obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
> obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
> diff --git a/drivers/net/xilinx_axi_mrmac.c b/drivers/net/xilinx_axi_mrmac.c
> new file mode 100644
> index 00..bffedf8280
> --- /dev/null
> +++ b/drivers/net/xilinx_axi_mrmac.c
> @@ -0,0 +1,525 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Xilinx Multirate Ethernet MAC(MRMAC) driver
> + *
> + * Author(s): Ashok Reddy Soma
> + * Michal Simek
> + *
> + * Copyright (C) 2021 Xilinx, Inc. All rights reserved.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include "xilinx_axi_mrmac.h"
> +
> +static u8 rxframe[RX_DESC * PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
> +static u8 txminframe[MIN_PKT_SIZE] __attribute((aligned(DMAALIGN)));
Please put this all in priv_auto
> +
> +/* Static buffer descriptors:
> + * MRMAC needs atleast two buffer descriptors for the TX/RX to happen.
> + * Otherwise MRMAC will drop the packets. So, have two tx and rx bd's here.
> + */
> +static struct mcdma_bd tx_bd[TX_DESC] __attribute((aligned(DMAALIGN)));
> +static struct mcdma_bd rx_bd[RX_DESC] __attribute((aligned(DMAALIGN)));
same here
> +
> +static void axi_mrmac_dma_write(struct mcdma_bd *bd, u32 *desc)
> +{
> + if (IS_ENABLED(CONFIG_PHYS_64BIT))
> + writeq((unsigned long)bd, desc);
> + else
> + writel((uintptr_t)bd, desc);
> +}
> +
> +static int axi_mrmac_ethernet_init(struct axi_mrmac_priv *priv)
function comment...what does it return?
> +{
> + struct mrmac_regs *regs = priv->iobase;
> + u32 val, reg;
> + u32 ret;
> +
> + /* Perform all the RESET's required */
> + val = readl(>reset);
> + val |= MRMAC_RX_SERDES_RST_MASK | MRMAC_TX_SERDES_RST_MASK |
> + MRMAC_RX_RST_MASK | MRMAC_TX_RST_MASK;
> + writel(val, >reset);
setbits_le32(>reset, ...)
Take a look at the other similar functions which can help in this driver.
> +
> + mdelay(MRMAC_RESET_DELAY);
> +
> + /* Configure Mode register */
> + reg = readl(>mode);
> +
> + debug("Configuring MRMAC speed to %d\n", priv->mrmac_rate);
> +
> + if (priv->mrmac_rate == SPEED_25000) {
> + reg &= ~MRMAC_CTL_RATE_CFG_MASK;
> + reg |= MRMAC_CTL_DATA_RATE_25G;
> + reg |= (MRMAC_CTL_AXIS_CFG_25G_IND <<
> MRMAC_CTL_AXIS_CFG_SHIFT);
> + reg |= (MRMAC_CTL_SERDES_WIDTH_25G <<
> +
[PATCH 2/3] net: xilinx: axi_mrmac: Add MRMAC driver
Add support for xilinx multirate(MRMAC) ethernet driver.
This driver uses multichannel DMA(MCDMA) for data transfers of MRMAC.
Added support for 4 ports of MRMAC for speeds 10G and 25G.
MCDMA supports upto 16 channels but in this driver we have setup only
one channel which is enough.
Tested 10G and 25G on all 4 ports.
Signed-off-by: Ashok Reddy Soma
---
MAINTAINERS| 1 +
drivers/net/Kconfig| 9 +
drivers/net/Makefile | 1 +
drivers/net/xilinx_axi_mrmac.c | 525 +
drivers/net/xilinx_axi_mrmac.h | 192
5 files changed, 728 insertions(+)
create mode 100644 drivers/net/xilinx_axi_mrmac.c
create mode 100644 drivers/net/xilinx_axi_mrmac.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 2accd1fb83..cc05e13968 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -543,6 +543,7 @@ M: Michal Simek
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-versal/
+F: drivers/net/xilinx_axi_mrmac.*
F: drivers/watchdog/xilinx_wwdt.c
N: (?
+ * Michal Simek
+ *
+ * Copyright (C) 2021 Xilinx, Inc. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "xilinx_axi_mrmac.h"
+
+static u8 rxframe[RX_DESC * PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
+static u8 txminframe[MIN_PKT_SIZE] __attribute((aligned(DMAALIGN)));
+
+/* Static buffer descriptors:
+ * MRMAC needs atleast two buffer descriptors for the TX/RX to happen.
+ * Otherwise MRMAC will drop the packets. So, have two tx and rx bd's here.
+ */
+static struct mcdma_bd tx_bd[TX_DESC] __attribute((aligned(DMAALIGN)));
+static struct mcdma_bd rx_bd[RX_DESC] __attribute((aligned(DMAALIGN)));
+
+static void axi_mrmac_dma_write(struct mcdma_bd *bd, u32 *desc)
+{
+ if (IS_ENABLED(CONFIG_PHYS_64BIT))
+ writeq((unsigned long)bd, desc);
+ else
+ writel((uintptr_t)bd, desc);
+}
+
+static int axi_mrmac_ethernet_init(struct axi_mrmac_priv *priv)
+{
+ struct mrmac_regs *regs = priv->iobase;
+ u32 val, reg;
+ u32 ret;
+
+ /* Perform all the RESET's required */
+ val = readl(>reset);
+ val |= MRMAC_RX_SERDES_RST_MASK | MRMAC_TX_SERDES_RST_MASK |
+ MRMAC_RX_RST_MASK | MRMAC_TX_RST_MASK;
+ writel(val, >reset);
+
+ mdelay(MRMAC_RESET_DELAY);
+
+ /* Configure Mode register */
+ reg = readl(>mode);
+
+ debug("Configuring MRMAC speed to %d\n", priv->mrmac_rate);
+
+ if (priv->mrmac_rate == SPEED_25000) {
+ reg &= ~MRMAC_CTL_RATE_CFG_MASK;
+ reg |= MRMAC_CTL_DATA_RATE_25G;
+ reg |= (MRMAC_CTL_AXIS_CFG_25G_IND << MRMAC_CTL_AXIS_CFG_SHIFT);
+ reg |= (MRMAC_CTL_SERDES_WIDTH_25G <<
+ MRMAC_CTL_SERDES_WIDTH_SHIFT);
+ } else {
+ reg &= ~MRMAC_CTL_RATE_CFG_MASK;
+ reg |= MRMAC_CTL_DATA_RATE_10G;
+ reg |= (MRMAC_CTL_AXIS_CFG_10G_IND << MRMAC_CTL_AXIS_CFG_SHIFT);
+ reg |= (MRMAC_CTL_SERDES_WIDTH_10G <<
+ MRMAC_CTL_SERDES_WIDTH_SHIFT);
+ }
+
+ /* For tick reg */
+ reg |= MRMAC_CTL_PM_TICK_MASK;
+ writel(reg, >mode);
+
+ val = readl(>reset);
+ val &= ~(MRMAC_RX_SERDES_RST_MASK | MRMAC_TX_SERDES_RST_MASK |
+MRMAC_RX_RST_MASK | MRMAC_TX_RST_MASK);
+ writel(val, >reset);
+
+ mdelay(MRMAC_RESET_DELAY);
+
+ /* Setup MRMAC hardware options */
+ writel(readl(>rx_config) | MRMAC_RX_DEL_FCS_MASK,
+ >rx_config);
+ writel(readl(>tx_config) | MRMAC_TX_INS_FCS_MASK,
+ >tx_config);
+ writel(readl(>tx_config) | MRMAC_TX_EN_MASK, >tx_config);
+ writel(readl(>rx_config) | MRMAC_RX_EN_MASK, >rx_config);
+
+ /* Check for block lock bit to be set. This ensures that
+* MRMAC ethernet IP is functioning normally.
+*/
+ writel(MRMAC_STS_ALL_MASK, (phys_addr_t)priv->iobase +
+ MRMAC_TX_STS_OFFSET);
+ writel(MRMAC_STS_ALL_MASK, (phys_addr_t)priv->iobase +
+ MRMAC_RX_STS_OFFSET);
+ writel(MRMAC_STS_ALL_MASK, (phys_addr_t)priv->iobase +
+ MRMAC_STATRX_BLKLCK_OFFSET);
+
+ ret = wait_for_bit_le32((u32 *)((phys_addr_t)priv->iobase +
+ MRMAC_STATRX_BLKLCK_OFFSET),
+ MRMAC_RX_BLKLCK_MASK, true,
+ MRMAC_BLKLCK_TIMEOUT, true);
+ if (ret) {
+ printf("%s: MRMAC block lock not complete!\n", __func__);
+ return 1;
+ }
+
+ writel(MRMAC_TICK_TRIGGER, >tick_reg);
+
+ return 0;
+}
+
+/* Reset DMA engine */
+static int axi_mcdma_init(struct axi_mrmac_priv *priv)
+{
+ u32 ret;
+
+ /* Reset the engine so the hardware starts
