Re: [PATCH 2/6 v4] spmi: msm: add arbiter version 5 support

2021-10-31 Thread Tom Rini 
On Sun, Oct 17, 2021 at 01:44:28PM +0300, Dzmitry Sankouski wrote:

> Currently driver supports only version 1 and 2.
> Version 5 has slightly different registers structure
> 
> Signed-off-by: Dzmitry Sankouski 
> Cc: Ramon Fried 
> Cc: Tom Rini 

Applied to u-boot/master, thanks!

-- 
Tom


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[PATCH 2/6 v4] spmi: msm: add arbiter version 5 support

2021-10-17 Thread Dzmitry Sankouski 
Currently driver supports only version 1 and 2.
Version 5 has slightly different registers structure

Signed-off-by: Dzmitry Sankouski 
Cc: Ramon Fried 
Cc: Tom Rini 
---
Changes for v2:
- change string formats in debug statements
Changes for v3:
- remove if else braces where possible
Changes for v4:
- change variable type to fix pointer cast warning

 MAINTAINERS |   1 +
 drivers/spmi/spmi-msm.c | 154 +++-
 2 files changed, 105 insertions(+), 50 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 52ddc99cda..6b8b0783d2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -392,6 +392,7 @@ F:  drivers/phy/msm8916-usbh-phy.c
 F: drivers/serial/serial_msm.c
 F: drivers/serial/serial_msm_geni.c
 F: drivers/smem/msm_smem.c
+F: drivers/spmi/spmi-msm.c
 F: drivers/usb/host/ehci-msm.c
 
 ARM STI
diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
index 5a335e50aa..27a035c0a5 100644
--- a/drivers/spmi/spmi-msm.c
+++ b/drivers/spmi/spmi-msm.c
@@ -19,39 +19,63 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* PMIC Arbiter configuration registers */
-#define PMIC_ARB_VERSION   0x
-#define PMIC_ARB_VERSION_V2_MIN0x2001
-
-#define ARB_CHANNEL_OFFSET(n)  (0x4 * (n))
-#define SPMI_CH_OFFSET(chnl)   ((chnl) * 0x8000)
-
-#define SPMI_REG_CMD0  0x0
-#define SPMI_REG_CONFIG0x4
-#define SPMI_REG_STATUS0x8
-#define SPMI_REG_WDATA 0x10
-#define SPMI_REG_RDATA 0x18
-
-#define SPMI_CMD_OPCODE_SHIFT  27
-#define SPMI_CMD_SLAVE_ID_SHIFT20
-#define SPMI_CMD_ADDR_SHIFT12
-#define SPMI_CMD_ADDR_OFFSET_SHIFT 4
-#define SPMI_CMD_BYTE_CNT_SHIFT0
-
-#define SPMI_CMD_EXT_REG_WRITE_LONG0x00
-#define SPMI_CMD_EXT_REG_READ_LONG 0x01
-
-#define SPMI_STATUS_DONE   0x1
+#define PMIC_ARB_VERSION 0x
+#define PMIC_ARB_VERSION_V2_MIN 0x2001
+#define PMIC_ARB_VERSION_V3_MIN 0x3000
+#define PMIC_ARB_VERSION_V5_MIN 0x5000
+
+#define APID_MAP_OFFSET_V1_V2_V3 (0x800)
+#define APID_MAP_OFFSET_V5 (0x900)
+#define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
+#define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
+#define SPMI_V5_OBS_CH_OFFSET(chnl) ((chnl) * 0x80)
+#define SPMI_V5_RW_CH_OFFSET(chnl) ((chnl) * 0x1)
+
+#define SPMI_REG_CMD0 0x0
+#define SPMI_REG_CONFIG 0x4
+#define SPMI_REG_STATUS 0x8
+#define SPMI_REG_WDATA 0x10
+#define SPMI_REG_RDATA 0x18
+
+#define SPMI_CMD_OPCODE_SHIFT 27
+#define SPMI_CMD_SLAVE_ID_SHIFT 20
+#define SPMI_CMD_ADDR_SHIFT 12
+#define SPMI_CMD_ADDR_OFFSET_SHIFT 4
+#define SPMI_CMD_BYTE_CNT_SHIFT 0
+
+#define SPMI_CMD_EXT_REG_WRITE_LONG 0x00
+#define SPMI_CMD_EXT_REG_READ_LONG 0x01
+
+#define SPMI_STATUS_DONE 0x1
+
+#define SPMI_MAX_CHANNELS 128
+#define SPMI_MAX_SLAVES 16
+#define SPMI_MAX_PERIPH 256
+
+enum arb_ver {
+   V1 = 1,
+   V2,
+   V3,
+   V5 = 5
+};
 
-#define SPMI_MAX_CHANNELS  128
-#define SPMI_MAX_SLAVES16
-#define SPMI_MAX_PERIPH256
+/*
+ * PMIC arbiter version 5 uses different register offsets for read/write vs
+ * observer channels.
+ */
+enum pmic_arb_channel {
+   PMIC_ARB_CHANNEL_RW,
+   PMIC_ARB_CHANNEL_OBS,
+};
 
 struct msm_spmi_priv {
-   phys_addr_t arb_chnl; /* ARB channel mapping base */
+   phys_addr_t arb_chnl;  /* ARB channel mapping base */
phys_addr_t spmi_core; /* SPMI core */
-   phys_addr_t spmi_obs; /* SPMI observer */
+   phys_addr_t spmi_obs;  /* SPMI observer */
/* SPMI channel map */
uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
+   /* SPMI bus arbiter version */
+   u32 arb_ver;
 };
 
 static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
@@ -59,6 +83,7 @@ static int msm_spmi_write(struct udevice *dev, int usid, int 
pid, int off,
 {
struct msm_spmi_priv *priv = dev_get_priv(dev);
unsigned channel;
+   unsigned int ch_offset;
uint32_t reg = 0;
 
if (usid >= SPMI_MAX_SLAVES)
@@ -69,8 +94,8 @@ static int msm_spmi_write(struct udevice *dev, int usid, int 
pid, int off,
channel = priv->channel_map[usid][pid];
 
/* Disable IRQ mode for the current channel*/
-   writel(0x0, priv->spmi_core + SPMI_CH_OFFSET(channel) +
-  SPMI_REG_CONFIG);
+   writel(0x0,
+  priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
 
/* Write single byte */
writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
@@ -82,6 +107,11 @@ static int msm_spmi_write(struct udevice *dev, int usid, 
int pid, int off,
reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
reg |= 1; /* byte count */
 
+   if (priv->arb_ver == V5)
+   ch_offset = SPMI_V5_RW_CH_OFFSET(channel);
+   else
+   ch_offset = SPMI_CH_OFFSET(channel);
+
/* Send write

Re: [PATCH 2/6 v4] spmi: msm: add arbiter version 5 support

2021-10-14 Thread Simon Glass 
On Fri, 8 Oct 2021 at 05:43, Dzmitry Sankouski  wrote:
>
> Currently driver supports only version 1 and 2.
> Version 5 has slightly different registers structure
>
> Signed-off-by: Dzmitry Sankouski 
> Cc: Ramon Fried 
> Cc: Tom Rini 
> ---
> Changes for v2:
> - change string formats in debug statements
> Changes for v3:
> - remove if else braces where possible
> Changes for v4:
> - change variable type to fix pointer cast warning
>
>  MAINTAINERS |   1 +
>  drivers/spmi/spmi-msm.c | 154 +++-
>  2 files changed, 105 insertions(+), 50 deletions(-)
>

Reviewed-by: Simon Glass

[PATCH 2/6 v4] spmi: msm: add arbiter version 5 support

2021-10-12 Thread Dzmitry Sankouski 
Currently driver supports only version 1 and 2.
Version 5 has slightly different registers structure

Signed-off-by: Dzmitry Sankouski 
Cc: Ramon Fried 
Cc: Tom Rini 
---
Changes for v2:
- change string formats in debug statements
Changes for v3:
- remove if else braces where possible
Changes for v4:
- change variable type to fix pointer cast warning

 MAINTAINERS |   1 +
 drivers/spmi/spmi-msm.c | 154 +++-
 2 files changed, 105 insertions(+), 50 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 52ddc99cda..6b8b0783d2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -392,6 +392,7 @@ F:  drivers/phy/msm8916-usbh-phy.c
 F: drivers/serial/serial_msm.c
 F: drivers/serial/serial_msm_geni.c
 F: drivers/smem/msm_smem.c
+F: drivers/spmi/spmi-msm.c
 F: drivers/usb/host/ehci-msm.c
 
 ARM STI
diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
index 5a335e50aa..27a035c0a5 100644
--- a/drivers/spmi/spmi-msm.c
+++ b/drivers/spmi/spmi-msm.c
@@ -19,39 +19,63 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* PMIC Arbiter configuration registers */
-#define PMIC_ARB_VERSION   0x
-#define PMIC_ARB_VERSION_V2_MIN0x2001
-
-#define ARB_CHANNEL_OFFSET(n)  (0x4 * (n))
-#define SPMI_CH_OFFSET(chnl)   ((chnl) * 0x8000)
-
-#define SPMI_REG_CMD0  0x0
-#define SPMI_REG_CONFIG0x4
-#define SPMI_REG_STATUS0x8
-#define SPMI_REG_WDATA 0x10
-#define SPMI_REG_RDATA 0x18
-
-#define SPMI_CMD_OPCODE_SHIFT  27
-#define SPMI_CMD_SLAVE_ID_SHIFT20
-#define SPMI_CMD_ADDR_SHIFT12
-#define SPMI_CMD_ADDR_OFFSET_SHIFT 4
-#define SPMI_CMD_BYTE_CNT_SHIFT0
-
-#define SPMI_CMD_EXT_REG_WRITE_LONG0x00
-#define SPMI_CMD_EXT_REG_READ_LONG 0x01
-
-#define SPMI_STATUS_DONE   0x1
+#define PMIC_ARB_VERSION 0x
+#define PMIC_ARB_VERSION_V2_MIN 0x2001
+#define PMIC_ARB_VERSION_V3_MIN 0x3000
+#define PMIC_ARB_VERSION_V5_MIN 0x5000
+
+#define APID_MAP_OFFSET_V1_V2_V3 (0x800)
+#define APID_MAP_OFFSET_V5 (0x900)
+#define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
+#define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
+#define SPMI_V5_OBS_CH_OFFSET(chnl) ((chnl) * 0x80)
+#define SPMI_V5_RW_CH_OFFSET(chnl) ((chnl) * 0x1)
+
+#define SPMI_REG_CMD0 0x0
+#define SPMI_REG_CONFIG 0x4
+#define SPMI_REG_STATUS 0x8
+#define SPMI_REG_WDATA 0x10
+#define SPMI_REG_RDATA 0x18
+
+#define SPMI_CMD_OPCODE_SHIFT 27
+#define SPMI_CMD_SLAVE_ID_SHIFT 20
+#define SPMI_CMD_ADDR_SHIFT 12
+#define SPMI_CMD_ADDR_OFFSET_SHIFT 4
+#define SPMI_CMD_BYTE_CNT_SHIFT 0
+
+#define SPMI_CMD_EXT_REG_WRITE_LONG 0x00
+#define SPMI_CMD_EXT_REG_READ_LONG 0x01
+
+#define SPMI_STATUS_DONE 0x1
+
+#define SPMI_MAX_CHANNELS 128
+#define SPMI_MAX_SLAVES 16
+#define SPMI_MAX_PERIPH 256
+
+enum arb_ver {
+   V1 = 1,
+   V2,
+   V3,
+   V5 = 5
+};
 
-#define SPMI_MAX_CHANNELS  128
-#define SPMI_MAX_SLAVES16
-#define SPMI_MAX_PERIPH256
+/*
+ * PMIC arbiter version 5 uses different register offsets for read/write vs
+ * observer channels.
+ */
+enum pmic_arb_channel {
+   PMIC_ARB_CHANNEL_RW,
+   PMIC_ARB_CHANNEL_OBS,
+};
 
 struct msm_spmi_priv {
-   phys_addr_t arb_chnl; /* ARB channel mapping base */
+   phys_addr_t arb_chnl;  /* ARB channel mapping base */
phys_addr_t spmi_core; /* SPMI core */
-   phys_addr_t spmi_obs; /* SPMI observer */
+   phys_addr_t spmi_obs;  /* SPMI observer */
/* SPMI channel map */
uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
+   /* SPMI bus arbiter version */
+   u32 arb_ver;
 };
 
 static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
@@ -59,6 +83,7 @@ static int msm_spmi_write(struct udevice *dev, int usid, int 
pid, int off,
 {
struct msm_spmi_priv *priv = dev_get_priv(dev);
unsigned channel;
+   unsigned int ch_offset;
uint32_t reg = 0;
 
if (usid >= SPMI_MAX_SLAVES)
@@ -69,8 +94,8 @@ static int msm_spmi_write(struct udevice *dev, int usid, int 
pid, int off,
channel = priv->channel_map[usid][pid];
 
/* Disable IRQ mode for the current channel*/
-   writel(0x0, priv->spmi_core + SPMI_CH_OFFSET(channel) +
-  SPMI_REG_CONFIG);
+   writel(0x0,
+  priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
 
/* Write single byte */
writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
@@ -82,6 +107,11 @@ static int msm_spmi_write(struct udevice *dev, int usid, 
int pid, int off,
reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
reg |= 1; /* byte count */
 
+   if (priv->arb_ver == V5)
+   ch_offset = SPMI_V5_RW_CH_OFFSET(channel);
+   else
+   ch_offset = SPMI_CH_OFFSET(channel);
+
/* Send write

[PATCH 2/6 v4] spmi: msm: add arbiter version 5 support

2021-10-07 Thread Dzmitry Sankouski 
Currently driver supports only version 1 and 2.
Version 5 has slightly different registers structure

Signed-off-by: Dzmitry Sankouski 
Cc: Ramon Fried 
Cc: Tom Rini 
---
Changes for v2:
- change string formats in debug statements
Changes for v3:
- remove if else braces where possible
Changes for v4:
- change variable type to fix pointer cast warning

 MAINTAINERS |   1 +
 drivers/spmi/spmi-msm.c | 154 +++-
 2 files changed, 105 insertions(+), 50 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 52ddc99cda..6b8b0783d2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -392,6 +392,7 @@ F:  drivers/phy/msm8916-usbh-phy.c
 F: drivers/serial/serial_msm.c
 F: drivers/serial/serial_msm_geni.c
 F: drivers/smem/msm_smem.c
+F: drivers/spmi/spmi-msm.c
 F: drivers/usb/host/ehci-msm.c
 
 ARM STI
diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
index 5a335e50aa..27a035c0a5 100644
--- a/drivers/spmi/spmi-msm.c
+++ b/drivers/spmi/spmi-msm.c
@@ -19,39 +19,63 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* PMIC Arbiter configuration registers */
-#define PMIC_ARB_VERSION   0x
-#define PMIC_ARB_VERSION_V2_MIN0x2001
-
-#define ARB_CHANNEL_OFFSET(n)  (0x4 * (n))
-#define SPMI_CH_OFFSET(chnl)   ((chnl) * 0x8000)
-
-#define SPMI_REG_CMD0  0x0
-#define SPMI_REG_CONFIG0x4
-#define SPMI_REG_STATUS0x8
-#define SPMI_REG_WDATA 0x10
-#define SPMI_REG_RDATA 0x18
-
-#define SPMI_CMD_OPCODE_SHIFT  27
-#define SPMI_CMD_SLAVE_ID_SHIFT20
-#define SPMI_CMD_ADDR_SHIFT12
-#define SPMI_CMD_ADDR_OFFSET_SHIFT 4
-#define SPMI_CMD_BYTE_CNT_SHIFT0
-
-#define SPMI_CMD_EXT_REG_WRITE_LONG0x00
-#define SPMI_CMD_EXT_REG_READ_LONG 0x01
-
-#define SPMI_STATUS_DONE   0x1
+#define PMIC_ARB_VERSION 0x
+#define PMIC_ARB_VERSION_V2_MIN 0x2001
+#define PMIC_ARB_VERSION_V3_MIN 0x3000
+#define PMIC_ARB_VERSION_V5_MIN 0x5000
+
+#define APID_MAP_OFFSET_V1_V2_V3 (0x800)
+#define APID_MAP_OFFSET_V5 (0x900)
+#define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
+#define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
+#define SPMI_V5_OBS_CH_OFFSET(chnl) ((chnl) * 0x80)
+#define SPMI_V5_RW_CH_OFFSET(chnl) ((chnl) * 0x1)
+
+#define SPMI_REG_CMD0 0x0
+#define SPMI_REG_CONFIG 0x4
+#define SPMI_REG_STATUS 0x8
+#define SPMI_REG_WDATA 0x10
+#define SPMI_REG_RDATA 0x18
+
+#define SPMI_CMD_OPCODE_SHIFT 27
+#define SPMI_CMD_SLAVE_ID_SHIFT 20
+#define SPMI_CMD_ADDR_SHIFT 12
+#define SPMI_CMD_ADDR_OFFSET_SHIFT 4
+#define SPMI_CMD_BYTE_CNT_SHIFT 0
+
+#define SPMI_CMD_EXT_REG_WRITE_LONG 0x00
+#define SPMI_CMD_EXT_REG_READ_LONG 0x01
+
+#define SPMI_STATUS_DONE 0x1
+
+#define SPMI_MAX_CHANNELS 128
+#define SPMI_MAX_SLAVES 16
+#define SPMI_MAX_PERIPH 256
+
+enum arb_ver {
+   V1 = 1,
+   V2,
+   V3,
+   V5 = 5
+};
 
-#define SPMI_MAX_CHANNELS  128
-#define SPMI_MAX_SLAVES16
-#define SPMI_MAX_PERIPH256
+/*
+ * PMIC arbiter version 5 uses different register offsets for read/write vs
+ * observer channels.
+ */
+enum pmic_arb_channel {
+   PMIC_ARB_CHANNEL_RW,
+   PMIC_ARB_CHANNEL_OBS,
+};
 
 struct msm_spmi_priv {
-   phys_addr_t arb_chnl; /* ARB channel mapping base */
+   phys_addr_t arb_chnl;  /* ARB channel mapping base */
phys_addr_t spmi_core; /* SPMI core */
-   phys_addr_t spmi_obs; /* SPMI observer */
+   phys_addr_t spmi_obs;  /* SPMI observer */
/* SPMI channel map */
uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
+   /* SPMI bus arbiter version */
+   u32 arb_ver;
 };
 
 static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
@@ -59,6 +83,7 @@ static int msm_spmi_write(struct udevice *dev, int usid, int 
pid, int off,
 {
struct msm_spmi_priv *priv = dev_get_priv(dev);
unsigned channel;
+   unsigned int ch_offset;
uint32_t reg = 0;
 
if (usid >= SPMI_MAX_SLAVES)
@@ -69,8 +94,8 @@ static int msm_spmi_write(struct udevice *dev, int usid, int 
pid, int off,
channel = priv->channel_map[usid][pid];
 
/* Disable IRQ mode for the current channel*/
-   writel(0x0, priv->spmi_core + SPMI_CH_OFFSET(channel) +
-  SPMI_REG_CONFIG);
+   writel(0x0,
+  priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
 
/* Write single byte */
writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
@@ -82,6 +107,11 @@ static int msm_spmi_write(struct udevice *dev, int usid, 
int pid, int off,
reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
reg |= 1; /* byte count */
 
+   if (priv->arb_ver == V5)
+   ch_offset = SPMI_V5_RW_CH_OFFSET(channel);
+   else
+   ch_offset = SPMI_CH_OFFSET(channel);
+
/* Send write