Re: [PATCH 5/5] net: phy: marvell10g: Adapt Marvell 10G PHY driver from Linux
On Sun, Mar 19, 2023 at 7:08 PM Marek Vasut
wrote:
>
> Pull Marvell 10G PHY driver from Linux 6.1.y as of commit
> d6d29292640d3 ("net: phy: marvell10g: select host interface configuration")
> and heavily adapt to match U-Boot PHY framework. Support for
> hwmon is removed as is much other functionality which could
> not be tested, this results in much simpler driver which can
> only bring the PHY up and set MAC type.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: "Ariel D'Alessandro"
> Cc: "Marek Behún"
> Cc: Joe Hershberger
> Cc: Marek Vasut
> Cc: Michael Trimarchi
> Cc: Nate Drude
> Cc: Ramon Fried
> Cc: Simon Glass
> Cc: Stefan Roese
> Cc: Tim Harvey
> Cc: Vladimir Oltean
> ---
> drivers/net/phy/Kconfig | 5 +
> drivers/net/phy/Makefile | 1 +
> drivers/net/phy/marvell10g.c | 605 +++
> 3 files changed, 611 insertions(+)
> create mode 100644 drivers/net/phy/marvell10g.c
>
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index 6806e3c0903..24158776f52 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -174,6 +174,11 @@ config PHY_LXT
> config PHY_MARVELL
> bool "Marvell Ethernet PHYs support"
>
> +config PHY_MARVELL_10G
> + bool "Marvell Alaska 10Gbit PHYs"
> + help
> + Support for the Marvell Alaska MV88X3310 and compatible PHYs.
> +
> config PHY_MESON_GXL
> bool "Amlogic Meson GXL Internal PHY support"
>
> diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
> index 963d96e2bcb..85d17f109cd 100644
> --- a/drivers/net/phy/Makefile
> +++ b/drivers/net/phy/Makefile
> @@ -20,6 +20,7 @@ obj-$(CONFIG_PHY_DAVICOM) += davicom.o
> obj-$(CONFIG_PHY_ET1011C) += et1011c.o
> obj-$(CONFIG_PHY_LXT) += lxt.o
> obj-$(CONFIG_PHY_MARVELL) += marvell.o
> +obj-$(CONFIG_PHY_MARVELL_10G) += marvell10g.o
> obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o
> obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
> obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
> diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
> new file mode 100644
> index 000..9e64672f5ca
> --- /dev/null
> +++ b/drivers/net/phy/marvell10g.c
> @@ -0,0 +1,605 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Marvell 10G 88x3310 PHY driver
> + *
> + * Based upon the ID registers, this PHY appears to be a mixture of IPs
> + * from two different companies.
> + *
> + * There appears to be several different data paths through the PHY which
> + * are automatically managed by the PHY. The following has been determined
> + * via observation and experimentation for a setup using single-lane Serdes:
> + *
> + * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
> + * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
> + * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
> + *
> + * With XAUI, observation shows:
> + *
> + *XAUI PHYXS --
> + *
> + * and no switching of the host interface mode occurs.
> + *
> + * If both the fiber and copper ports are connected, the first to gain
> + * link takes priority and the other port is completely locked out.
> + */
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffe
> +#define MV_PHY_ALASKA_NBT_QUIRK_REV(MARVELL_PHY_ID_88X3310 | 0xa)
> +
> +#define MV_VERSION(a, b, c, d) ((a) << 24 | (b) << 16 | (c) << 8 | (d))
> +
> +enum {
> + MV_PMA_FW_VER0 = 0xc011,
> + MV_PMA_FW_VER1 = 0xc012,
> + MV_PMA_21X0_PORT_CTRL = 0xc04a,
> + MV_PMA_21X0_PORT_CTRL_SWRST = BIT(15),
> + MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 0x7,
> + MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0x0,
> + MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII= 0x1,
> + MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII= 0x2,
> + MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 0x4,
> + MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 0x5,
> + MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
> + MV_PMA_BOOT = 0xc050,
> + MV_PMA_BOOT_FATAL = BIT(0),
> +
> + MV_PCS_BASE_T = 0x,
> + MV_PCS_BASE_R = 0x1000,
> + MV_PCS_1000BASEX= 0x2000,
> +
> + MV_PCS_CSCR1= 0x8000,
> + MV_PCS_CSCR1_ED_MASK= 0x0300,
> + MV_PCS_CSCR1_ED_OFF = 0x,
> + MV_PCS_CSCR1_ED_RX = 0x0200,
> + MV_PCS_CSCR1_ED_NLP = 0x0300,
> + MV_PCS_CSCR1_MDIX_MASK = 0x0060,
> + MV_PCS_CSCR1_MDIX_MDI = 0x,
> + MV_PCS_CSCR1_MDIX_MDIX = 0x0020,
> + MV_PCS_CSCR1_MDIX_AUTO = 0x0060,
> +
> + MV_PCS_DSC1 = 0x8003,
> + MV_PCS_DSC1_ENABLE = BIT(9),
> +
[PATCH 5/5] net: phy: marvell10g: Adapt Marvell 10G PHY driver from Linux
Pull Marvell 10G PHY driver from Linux 6.1.y as of commit
d6d29292640d3 ("net: phy: marvell10g: select host interface configuration")
and heavily adapt to match U-Boot PHY framework. Support for
hwmon is removed as is much other functionality which could
not be tested, this results in much simpler driver which can
only bring the PHY up and set MAC type.
Signed-off-by: Marek Vasut
---
Cc: "Ariel D'Alessandro"
Cc: "Marek Behún"
Cc: Joe Hershberger
Cc: Marek Vasut
Cc: Michael Trimarchi
Cc: Nate Drude
Cc: Ramon Fried
Cc: Simon Glass
Cc: Stefan Roese
Cc: Tim Harvey
Cc: Vladimir Oltean
---
drivers/net/phy/Kconfig | 5 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/marvell10g.c | 605 +++
3 files changed, 611 insertions(+)
create mode 100644 drivers/net/phy/marvell10g.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 6806e3c0903..24158776f52 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -174,6 +174,11 @@ config PHY_LXT
config PHY_MARVELL
bool "Marvell Ethernet PHYs support"
+config PHY_MARVELL_10G
+ bool "Marvell Alaska 10Gbit PHYs"
+ help
+ Support for the Marvell Alaska MV88X3310 and compatible PHYs.
+
config PHY_MESON_GXL
bool "Amlogic Meson GXL Internal PHY support"
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 963d96e2bcb..85d17f109cd 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PHY_DAVICOM) += davicom.o
obj-$(CONFIG_PHY_ET1011C) += et1011c.o
obj-$(CONFIG_PHY_LXT) += lxt.o
obj-$(CONFIG_PHY_MARVELL) += marvell.o
+obj-$(CONFIG_PHY_MARVELL_10G) += marvell10g.o
obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o
obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
new file mode 100644
index 000..9e64672f5ca
--- /dev/null
+++ b/drivers/net/phy/marvell10g.c
@@ -0,0 +1,605 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Marvell 10G 88x3310 PHY driver
+ *
+ * Based upon the ID registers, this PHY appears to be a mixture of IPs
+ * from two different companies.
+ *
+ * There appears to be several different data paths through the PHY which
+ * are automatically managed by the PHY. The following has been determined
+ * via observation and experimentation for a setup using single-lane Serdes:
+ *
+ * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
+ * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
+ * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
+ *
+ * With XAUI, observation shows:
+ *
+ *XAUI PHYXS --
+ *
+ * and no switching of the host interface mode occurs.
+ *
+ * If both the fiber and copper ports are connected, the first to gain
+ * link takes priority and the other port is completely locked out.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffe
+#define MV_PHY_ALASKA_NBT_QUIRK_REV(MARVELL_PHY_ID_88X3310 | 0xa)
+
+#define MV_VERSION(a, b, c, d) ((a) << 24 | (b) << 16 | (c) << 8 | (d))
+
+enum {
+ MV_PMA_FW_VER0 = 0xc011,
+ MV_PMA_FW_VER1 = 0xc012,
+ MV_PMA_21X0_PORT_CTRL = 0xc04a,
+ MV_PMA_21X0_PORT_CTRL_SWRST = BIT(15),
+ MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 0x7,
+ MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0x0,
+ MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII= 0x1,
+ MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII= 0x2,
+ MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 0x4,
+ MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 0x5,
+ MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
+ MV_PMA_BOOT = 0xc050,
+ MV_PMA_BOOT_FATAL = BIT(0),
+
+ MV_PCS_BASE_T = 0x,
+ MV_PCS_BASE_R = 0x1000,
+ MV_PCS_1000BASEX= 0x2000,
+
+ MV_PCS_CSCR1= 0x8000,
+ MV_PCS_CSCR1_ED_MASK= 0x0300,
+ MV_PCS_CSCR1_ED_OFF = 0x,
+ MV_PCS_CSCR1_ED_RX = 0x0200,
+ MV_PCS_CSCR1_ED_NLP = 0x0300,
+ MV_PCS_CSCR1_MDIX_MASK = 0x0060,
+ MV_PCS_CSCR1_MDIX_MDI = 0x,
+ MV_PCS_CSCR1_MDIX_MDIX = 0x0020,
+ MV_PCS_CSCR1_MDIX_AUTO = 0x0060,
+
+ MV_PCS_DSC1 = 0x8003,
+ MV_PCS_DSC1_ENABLE = BIT(9),
+ MV_PCS_DSC1_10GBT = 0x01c0,
+ MV_PCS_DSC1_1GBR= 0x0038,
+ MV_PCS_DSC1_100BTX = 0x0007,
+ MV_PCS_DSC2 = 0x8004,
+ MV_PCS_DSC2_2P5G= 0xf000,
+ MV_PCS_DSC2_5G = 0x0f00,
+
+ MV_PCS_CSSR1= 0x8008,
+ MV_PCS_CSSR1_SPD1_MASK
