[PATCH RFC 2/2] clk: add clock framework for HiSilicon SoCs

[Yang Xiwen via B4 Relay]

From: Yang Xiwen 

Hi3798 Series SoCs have a CRG (Clock Reset Generator) module which
manages all clocks and resets of the SoC.

The first supported chip is Hi3798MV200.  The unused clocks are not
registered to save space and time. Only necessary clocks are
implemented right now.

Signed-off-by: Yang Xiwen 
---
 drivers/clk/Kconfig |   7 ++
 drivers/clk/Makefile|   1 +
 drivers/clk/hisilicon/Kconfig   |  14 +++
 drivers/clk/hisilicon/Makefile  |   8 ++
 drivers/clk/hisilicon/clk-hi3798mv200.c | 213 
 drivers/clk/hisilicon/clk.c | 102 +++
 drivers/clk/hisilicon/clk.h |  55 +
 include/dt-bindings/clock/histb-clock.h |   4 +
 8 files changed, 404 insertions(+)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 017dd260a5..4c5ac46b26 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -127,6 +127,12 @@ config CLK_ICS8N3QV01
  Crystal Oscillator). The output frequency can be programmed via an
  I2C interface.
 
+config CLK_HISI
+   bool "Enable Hisilicon Clock Framework"
+   depends on CLK && CLK_CCF
+   help
+ Support for Hisilicon Clock Framework.
+
 config CLK_INTEL
bool "Enable clock driver for Intel x86"
depends on CLK && X86
@@ -249,6 +255,7 @@ config CLK_ZYNQMP
 source "drivers/clk/analogbits/Kconfig"
 source "drivers/clk/at91/Kconfig"
 source "drivers/clk/exynos/Kconfig"
+source "drivers/clk/hisilicon/Kconfig"
 source "drivers/clk/imx/Kconfig"
 source "drivers/clk/meson/Kconfig"
 source "drivers/clk/microchip/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 638ad04bae..90e7e1b5f4 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
 obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
 obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
 obj-$(CONFIG_CLK_EXYNOS) += exynos/
+obj-$(CONFIG_CLK_HISI) += hisilicon/
 obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
 obj-$(CONFIG_CLK_K210) += clk_k210.o
 obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 00..caa51b7831
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+if CLK_HISI
+menu "HiSilicon CRG Driver"
+
+config COMMON_CLK_HI3798MV200
+   tristate "Hi3798MV200 CRG Driver"
+   select RESET_HISILICON
+   depends on ARCH_HISTB
+   help
+ Build the CRG driver for Hi3798MV200.
+
+endmenu
+endif
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
new file mode 100644
index 00..85a0ffb4a1
--- /dev/null
+++ b/drivers/clk/hisilicon/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Hisilicon Clock specific Makefile
+#
+
+obj-y  += clk.o
+
+obj-$(CONFIG_COMMON_CLK_HI3798MV200)   += clk-hi3798mv200.o
diff --git a/drivers/clk/hisilicon/clk-hi3798mv200.c 
b/drivers/clk/hisilicon/clk-hi3798mv200.c
new file mode 100644
index 00..01bb20d940
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3798mv200.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Hi3798MV200 Clock and Reset Generator Driver.
+ * Adapted from clk-hi3798cv200.c.
+ *
+ * Copyright (c) 2024 Yang Xiwen 
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk.h"
+
+/* hi3798MV200 core CRG */
+#define HI3798MV200_INNER_CLK_OFFSET   64
+#define HI3798MV200_FIXED_12M  65
+#define HI3798MV200_FIXED_24M  66
+#define HI3798MV200_FIXED_25M  67
+#define HI3798MV200_FIXED_27M  68
+#define HI3798MV200_FIXED_48M  69
+#define HI3798MV200_FIXED_50M  70
+#define HI3798MV200_FIXED_54M  71
+#define HI3798MV200_FIXED_60M  72
+#define HI3798MV200_FIXED_75M  73
+#define HI3798MV200_FIXED_100M 74
+#define HI3798MV200_FIXED_150M 75
+#define HI3798MV200_FIXED_166P5M   76
+#define HI3798MV200_FIXED_200M 77
+#define HI3798MV200_FIXED_250M 78
+#define HI3798MV200_FIXED_300M 79
+#define HI3798MV200_FIXED_400M 80
+#define HI3798MV200_MMC_MUX81
+#define HI3798MV200_COMBPHY1_MUX   82
+#define HI3798MV200_SDIO0_MUX  83
+#define HI3798MV200_COMBPHY0_MUX   84
+#define HI3798MV200_SDIO1_MUX  85
+#define HI3798MV200_ETH_MUX86
+
+static const struct hisi_fixed_rate_clock hi3798mv200_fixed_rate_clks[] = {
+   { HISTB_OSC_CLK, "clk_osc", 2400, },
+   { HISTB_APB_CLK, "clk_apb", 1, },
+   { HISTB_AHB_CLK, "clk_ahb", 2, },
+   { HI3798MV200_FIXED_12M, "12m", 

[PATCH RFC 2/2] clk: add clock framework for HiSilicon SoCs

[Yang Xiwen via B4 Relay]

From: Yang Xiwen 

Hi3798 Series SoCs have a CRG (Clock Reset Generator) module which
manages all clocks and resets of the SoC.

The first supported chip is Hi3798MV200.  The unused clocks are not
registered to save space and time. Only necessary clocks are
implemented right now.

Signed-off-by: Yang Xiwen 
---
 drivers/clk/Kconfig |   7 ++
 drivers/clk/Makefile|   1 +
 drivers/clk/hisilicon/Kconfig   |  14 +++
 drivers/clk/hisilicon/Makefile  |   8 ++
 drivers/clk/hisilicon/clk-hi3798mv200.c | 213 
 drivers/clk/hisilicon/clk.c | 102 +++
 drivers/clk/hisilicon/clk.h |  55 +
 include/dt-bindings/clock/histb-clock.h |   4 +
 8 files changed, 404 insertions(+)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 017dd260a5..4c5ac46b26 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -127,6 +127,12 @@ config CLK_ICS8N3QV01
  Crystal Oscillator). The output frequency can be programmed via an
  I2C interface.
 
+config CLK_HISI
+   bool "Enable Hisilicon Clock Framework"
+   depends on CLK && CLK_CCF
+   help
+ Support for Hisilicon Clock Framework.
+
 config CLK_INTEL
bool "Enable clock driver for Intel x86"
depends on CLK && X86
@@ -249,6 +255,7 @@ config CLK_ZYNQMP
 source "drivers/clk/analogbits/Kconfig"
 source "drivers/clk/at91/Kconfig"
 source "drivers/clk/exynos/Kconfig"
+source "drivers/clk/hisilicon/Kconfig"
 source "drivers/clk/imx/Kconfig"
 source "drivers/clk/meson/Kconfig"
 source "drivers/clk/microchip/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 638ad04bae..90e7e1b5f4 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
 obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
 obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
 obj-$(CONFIG_CLK_EXYNOS) += exynos/
+obj-$(CONFIG_CLK_HISI) += hisilicon/
 obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
 obj-$(CONFIG_CLK_K210) += clk_k210.o
 obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 00..caa51b7831
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+if CLK_HISI
+menu "HiSilicon CRG Driver"
+
+config COMMON_CLK_HI3798MV200
+   tristate "Hi3798MV200 CRG Driver"
+   select RESET_HISILICON
+   depends on ARCH_HISTB
+   help
+ Build the CRG driver for Hi3798MV200.
+
+endmenu
+endif
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
new file mode 100644
index 00..85a0ffb4a1
--- /dev/null
+++ b/drivers/clk/hisilicon/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Hisilicon Clock specific Makefile
+#
+
+obj-y  += clk.o
+
+obj-$(CONFIG_COMMON_CLK_HI3798MV200)   += clk-hi3798mv200.o
diff --git a/drivers/clk/hisilicon/clk-hi3798mv200.c 
b/drivers/clk/hisilicon/clk-hi3798mv200.c
new file mode 100644
index 00..01bb20d940
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3798mv200.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Hi3798MV200 Clock and Reset Generator Driver.
+ * Adapted from clk-hi3798cv200.c.
+ *
+ * Copyright (c) 2024 Yang Xiwen 
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk.h"
+
+/* hi3798MV200 core CRG */
+#define HI3798MV200_INNER_CLK_OFFSET   64
+#define HI3798MV200_FIXED_12M  65
+#define HI3798MV200_FIXED_24M  66
+#define HI3798MV200_FIXED_25M  67
+#define HI3798MV200_FIXED_27M  68
+#define HI3798MV200_FIXED_48M  69
+#define HI3798MV200_FIXED_50M  70
+#define HI3798MV200_FIXED_54M  71
+#define HI3798MV200_FIXED_60M  72
+#define HI3798MV200_FIXED_75M  73
+#define HI3798MV200_FIXED_100M 74
+#define HI3798MV200_FIXED_150M 75
+#define HI3798MV200_FIXED_166P5M   76
+#define HI3798MV200_FIXED_200M 77
+#define HI3798MV200_FIXED_250M 78
+#define HI3798MV200_FIXED_300M 79
+#define HI3798MV200_FIXED_400M 80
+#define HI3798MV200_MMC_MUX81
+#define HI3798MV200_COMBPHY1_MUX   82
+#define HI3798MV200_SDIO0_MUX  83
+#define HI3798MV200_COMBPHY0_MUX   84
+#define HI3798MV200_SDIO1_MUX  85
+#define HI3798MV200_ETH_MUX86
+
+static const struct hisi_fixed_rate_clock hi3798mv200_fixed_rate_clks[] = {
+   { HISTB_OSC_CLK, "clk_osc", 2400, },
+   { HISTB_APB_CLK, "clk_apb", 1, },
+   { HISTB_AHB_CLK, "clk_ahb", 2, },
+   { HI3798MV200_FIXED_12M, "12m",