Re: [PATCH V2] clk: clk_versaclock: Add support for versaclock driver
On 6/3/21 8:28 AM, Adam Ford wrote: > The driver is based on the Versaclock driver from the Linux code, but > due to the differences in the clock API between U-Boot and Linux, some > pieces had to be changed. > > This driver creates a mux, pfd, pll, and a series of fod ouputs. > Rate Usecnt Name > -- > 2500 0`-- x304-clock > 2500 0`-- clock-control...@6a.mux > 2500 0|-- clock-control...@6a.pfd > 28 0| `-- clock-control...@6a.pll > 0| |-- clock-controller@6a.fod0 > 0| | `-- clock-controller@6a.out1 > 0| |-- clock-controller@6a.fod1 > 0| | `-- clock-controller@6a.out2 > 5000 0| |-- clock-controller@6a.fod2 > 5000 0| | `-- clock-controller@6a.out3 > 125000| `-- clock-controller@6a.fod3 > 125000| `-- clock-controller@6a.out4 > 2500 0`-- clock-controller@6a.out0_sel_i2cb > > A translation function is added so the references to < X> get routed > to the corresponding clock-control...@6a.outx. > > Signed-off-by: Adam Ford > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig > index 40a5a5dd88..2a7507ea18 100644 > --- a/drivers/clk/Kconfig > +++ b/drivers/clk/Kconfig > @@ -197,4 +197,13 @@ config SANDBOX_CLK_CCF > Enable this option if you want to test the Linux kernel's Common > Clock Framework [CCF] code in U-Boot's Sandbox clock driver. > > +config CLK_VERSACLOCK > + tristate "Enable VersaClock 5/6 devices" > + depends on CLK > + depends on CLK_CCF > + depends on OF_CONTROL > + help > +This driver supports the IDT VersaClock 5 and VersaClock 6 > +programmable clock generators. > + > endmenu > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile > index 645709b855..6f5ddafd64 100644 > --- a/drivers/clk/Makefile > +++ b/drivers/clk/Makefile > @@ -51,3 +51,4 @@ obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o > obj-$(CONFIG_STM32H7) += clk_stm32h7.o > obj-$(CONFIG_CLK_VERSAL) += clk_versal.o > obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o > +obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o > diff --git a/drivers/clk/clk_versaclock.c b/drivers/clk/clk_versaclock.c > new file mode 100644 > index 00..ee5562978a > --- /dev/null > +++ b/drivers/clk/clk_versaclock.c > @@ -0,0 +1,979 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +/* > + * Driver for IDT Versaclock 5/6 > + * > + * Derived from code Copyright (C) 2017 Marek Vasut > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +/* Configuration register block */ > +#define VC5_PRIM_SRC_SHDN 0x10 > +#define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7) > +#define VC5_PRIM_SRC_SHDN_EN_CLKINBIT(6) > +#define VC5_XTAL_X1_LOAD_CAP 0x12 > +#define VC5_XTAL_X2_LOAD_CAP 0x13 > +#define VC5_REF_DIVIDER 0x15 > +#define VC5_REF_DIVIDER_SEL_PREDIV2 BIT(7) > +#define VC5_REF_DIVIDER_REF_DIV(n)((n) & 0x3f) > +#define VC5_VCO_CTRL_AND_PREDIV 0x16 > +#define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV BIT(7) > +#define VC5_FEEDBACK_INT_DIV 0x17 > + > +/* Output divider control for divider 1,2,3,4 */ > +#define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10)) > +#define VC5_OUT_DIV_CONTROL_RESET BIT(7) > +#define VC5_OUT_DIV_CONTROL_SELB_NORM BIT(3) > +#define VC5_OUT_DIV_CONTROL_SEL_EXT BIT(2) > +#define VC5_OUT_DIV_CONTROL_EN_FODBIT(0) > +#define VC5_OUT_DIV_FRAC(idx, n) (0x22 + ((idx) * 0x10) + (n)) > +#define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n)) > + > +/* Clock control register for clock 1,2 */ > +#define VC5_CLK_OUTPUT_CFG(idx, n)(0x60 + ((idx) * 0x2) + (n)) > +#define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5 > +#define VC5_CLK_OUTPUT_CFG0_CFG_MASK GENMASK(7, VC5_CLK_OUTPUT_CFG0_CFG_SHIFT) > +#define VC5_CLK_OUTPUT_CFG0_CFG_LVPECL(VC5_LVPECL) > +#define VC5_CLK_OUTPUT_CFG0_CFG_CMOS (VC5_CMOS) > +#define VC5_CLK_OUTPUT_CFG0_CFG_HCSL33(VC5_HCSL33) > +#define VC5_CLK_OUTPUT_CFG0_CFG_LVDS (VC5_LVDS) > +#define VC5_CLK_OUTPUT_CFG0_CFG_CMOS2 (VC5_CMOS2) > +#define VC5_CLK_OUTPUT_CFG0_CFG_CMOSD (VC5_CMOSD) > +#define VC5_CLK_OUTPUT_CFG0_CFG_HCSL25(VC5_HCSL25) > +#define VC5_CLK_OUTPUT_CFG0_PWR_SHIFT 3 > +#define VC5_CLK_OUTPUT_CFG0_PWR_MASK GENMASK(4,
[PATCH V2] clk: clk_versaclock: Add support for versaclock driver
The driver is based on the Versaclock driver from the Linux code, but due to the differences in the clock API between U-Boot and Linux, some pieces had to be changed. This driver creates a mux, pfd, pll, and a series of fod ouputs. Rate Usecnt Name -- 2500 0`-- x304-clock 2500 0`-- clock-control...@6a.mux 2500 0|-- clock-control...@6a.pfd 28 0| `-- clock-control...@6a.pll 0| |-- clock-controller@6a.fod0 0| | `-- clock-controller@6a.out1 0| |-- clock-controller@6a.fod1 0| | `-- clock-controller@6a.out2 5000 0| |-- clock-controller@6a.fod2 5000 0| | `-- clock-controller@6a.out3 125000| `-- clock-controller@6a.fod3 125000| `-- clock-controller@6a.out4 2500 0`-- clock-controller@6a.out0_sel_i2cb A translation function is added so the references to < X> get routed to the corresponding clock-control...@6a.outx. Signed-off-by: Adam Ford diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 40a5a5dd88..2a7507ea18 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -197,4 +197,13 @@ config SANDBOX_CLK_CCF Enable this option if you want to test the Linux kernel's Common Clock Framework [CCF] code in U-Boot's Sandbox clock driver. +config CLK_VERSACLOCK + tristate "Enable VersaClock 5/6 devices" + depends on CLK + depends on CLK_CCF + depends on OF_CONTROL + help + This driver supports the IDT VersaClock 5 and VersaClock 6 + programmable clock generators. + endmenu diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 645709b855..6f5ddafd64 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -51,3 +51,4 @@ obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o obj-$(CONFIG_STM32H7) += clk_stm32h7.o obj-$(CONFIG_CLK_VERSAL) += clk_versal.o obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o +obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o diff --git a/drivers/clk/clk_versaclock.c b/drivers/clk/clk_versaclock.c new file mode 100644 index 00..ee5562978a --- /dev/null +++ b/drivers/clk/clk_versaclock.c @@ -0,0 +1,979 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Driver for IDT Versaclock 5/6 + * + * Derived from code Copyright (C) 2017 Marek Vasut + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Configuration register block */ +#define VC5_PRIM_SRC_SHDN 0x10 +#define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7) +#define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6) +#define VC5_XTAL_X1_LOAD_CAP 0x12 +#define VC5_XTAL_X2_LOAD_CAP 0x13 +#define VC5_REF_DIVIDER0x15 +#define VC5_REF_DIVIDER_SEL_PREDIV2BIT(7) +#define VC5_REF_DIVIDER_REF_DIV(n) ((n) & 0x3f) +#define VC5_VCO_CTRL_AND_PREDIV0x16 +#define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV BIT(7) +#define VC5_FEEDBACK_INT_DIV 0x17 + +/* Output divider control for divider 1,2,3,4 */ +#define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10)) +#define VC5_OUT_DIV_CONTROL_RESET BIT(7) +#define VC5_OUT_DIV_CONTROL_SELB_NORM BIT(3) +#define VC5_OUT_DIV_CONTROL_SEL_EXTBIT(2) +#define VC5_OUT_DIV_CONTROL_EN_FOD BIT(0) +#define VC5_OUT_DIV_FRAC(idx, n) (0x22 + ((idx) * 0x10) + (n)) +#define VC5_OUT_DIV_INT(idx, n)(0x2d + ((idx) * 0x10) + (n)) + +/* Clock control register for clock 1,2 */ +#define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n)) +#define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5 +#define VC5_CLK_OUTPUT_CFG0_CFG_MASK GENMASK(7, VC5_CLK_OUTPUT_CFG0_CFG_SHIFT) +#define VC5_CLK_OUTPUT_CFG0_CFG_LVPECL (VC5_LVPECL) +#define VC5_CLK_OUTPUT_CFG0_CFG_CMOS (VC5_CMOS) +#define VC5_CLK_OUTPUT_CFG0_CFG_HCSL33 (VC5_HCSL33) +#define VC5_CLK_OUTPUT_CFG0_CFG_LVDS (VC5_LVDS) +#define VC5_CLK_OUTPUT_CFG0_CFG_CMOS2 (VC5_CMOS2) +#define VC5_CLK_OUTPUT_CFG0_CFG_CMOSD (VC5_CMOSD) +#define VC5_CLK_OUTPUT_CFG0_CFG_HCSL25 (VC5_HCSL25) +#define VC5_CLK_OUTPUT_CFG0_PWR_SHIFT 3 +#define VC5_CLK_OUTPUT_CFG0_PWR_MASK GENMASK(4, VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) +#define VC5_CLK_OUTPUT_CFG0_PWR_18 (0 << VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) +#define VC5_CLK_OUTPUT_CFG0_PWR_25 (2 << VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) +#define VC5_CLK_OUTPUT_CFG0_PWR_33 (3 << VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) +#define
