[PATCH v1] board: toradex: verdin-imx8mm: set fixed LPDDR4 refresh rate as per errata ERR050805
> From: Andrejs Cainikovs > Update lpddr4 configuration and training using updated spreadsheet and > tools from NXP using data from previous spreadsheet and verified > toward datasheet: > - MX8M_Mini_LPDDR4_RPA_v22.xlsx > - mscale_ddr_tool_v3.31_setup.exe > The most relevant update is related to errata ERR050805: > "DRAM: Controller automatic derating logic may not work when > the LPDDR4 memory temperature is above 85 °C at initialization" > Other relevant fixes: > - DRAMTMG7 register: corrected calculation of T_CKPDX parameter > (equal to tCKCKEH for LPDDR4) > - RANKCTL register: corrected calculations for ODTLon and ODTLoff > to follow the JEDEC specification > - ADDRMAP7 register: added support for 17-row devices > As per errata ERR050805: > An issue exists with the automatic derating logic of the DDR > controller that only samples the LPDDR4 MR4 register when the > Temperature Update Flag (TUF) field (MR4[7] ) is 1’b1. If the > LPDDR4 memory is initialized and starts operation above 85 °C > (MR4[2:0] > 3’b011), the MR4 Temperature Update Flag (TUF) will > not be set. The DDR Controller will therefore not automatically > adjust the memory refresh rate or de-rate memory timings based > on the LPDDR4 memory temperature. This may cause the controller > incorrectly setting the refresh period, potentially cause the > LPDDR4 memory losing data contents and lead to possible data > integrity issues above 85 °C. > Errata provides three possible workaround options, while option 2 > is the most reasonable: > Disable the automatic derating logic of the DDR controller and > apply fixed x2 refresh rate (0.5x refresh). This option is > suitable for designs that are expected to boot at or above 85 °C > and memory’s MR4[2:0] (Refresh Rate) DOES NOT report the following > conditions: > 3b101: 0.25x refresh, no de-rating > 3b110: 0.25x refresh, with de-rating > 3b111: SDRAM High temperature operating limit exceeded > [1]: https://www.nxp.com/docs/en/errata/IMX8MM_0N87W.pdf > Signed-off-by: Andrejs Cainikovs > Acked-by: Marcel Ziswiler > Reviewed-by: Fabio Estevam Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH,Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, 82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
Re: [PATCH v1] board: toradex: verdin-imx8mm: set fixed LPDDR4 refresh rate as per errata ERR050805
On Thu, Sep 28, 2023 at 11:57 AM Andrejs Cainikovs wrote: > > From: Andrejs Cainikovs > > Update lpddr4 configuration and training using updated spreadsheet and > tools from NXP using data from previous spreadsheet and verified > toward datasheet: > > - MX8M_Mini_LPDDR4_RPA_v22.xlsx > - mscale_ddr_tool_v3.31_setup.exe > > The most relevant update is related to errata ERR050805: > "DRAM: Controller automatic derating logic may not work when > the LPDDR4 memory temperature is above 85 °C at initialization" > > Other relevant fixes: > - DRAMTMG7 register: corrected calculation of T_CKPDX parameter > (equal to tCKCKEH for LPDDR4) > - RANKCTL register: corrected calculations for ODTLon and ODTLoff > to follow the JEDEC specification > - ADDRMAP7 register: added support for 17-row devices > > As per errata ERR050805: > > An issue exists with the automatic derating logic of the DDR > controller that only samples the LPDDR4 MR4 register when the > Temperature Update Flag (TUF) field (MR4[7] ) is 1’b1. If the > LPDDR4 memory is initialized and starts operation above 85 °C > (MR4[2:0] > 3’b011), the MR4 Temperature Update Flag (TUF) will > not be set. The DDR Controller will therefore not automatically > adjust the memory refresh rate or de-rate memory timings based > on the LPDDR4 memory temperature. This may cause the controller > incorrectly setting the refresh period, potentially cause the > LPDDR4 memory losing data contents and lead to possible data > integrity issues above 85 °C. > > Errata provides three possible workaround options, while option 2 > is the most reasonable: > > Disable the automatic derating logic of the DDR controller and > apply fixed x2 refresh rate (0.5x refresh). This option is > suitable for designs that are expected to boot at or above 85 °C > and memory’s MR4[2:0] (Refresh Rate) DOES NOT report the following > conditions: > 3b101: 0.25x refresh, no de-rating > 3b110: 0.25x refresh, with de-rating > 3b111: SDRAM High temperature operating limit exceeded > > [1]: https://www.nxp.com/docs/en/errata/IMX8MM_0N87W.pdf > > Signed-off-by: Andrejs Cainikovs Reviewed-by: Fabio Estevam
Re: [PATCH v1] board: toradex: verdin-imx8mm: set fixed LPDDR4 refresh rate as per errata ERR050805
On Thu, 2023-09-28 at 16:39 +0200, Andrejs Cainikovs wrote:
> From: Andrejs Cainikovs
>
> Update lpddr4 configuration and training using updated spreadsheet and
> tools from NXP using data from previous spreadsheet and verified
> toward datasheet:
>
> - MX8M_Mini_LPDDR4_RPA_v22.xlsx
> - mscale_ddr_tool_v3.31_setup.exe
>
> The most relevant update is related to errata ERR050805:
> "DRAM: Controller automatic derating logic may not work when
> the LPDDR4 memory temperature is above 85 °C at initialization"
>
> Other relevant fixes:
> - DRAMTMG7 register: corrected calculation of T_CKPDX parameter
> (equal to tCKCKEH for LPDDR4)
> - RANKCTL register: corrected calculations for ODTLon and ODTLoff
> to follow the JEDEC specification
> - ADDRMAP7 register: added support for 17-row devices
>
> As per errata ERR050805:
>
> An issue exists with the automatic derating logic of the DDR
> controller that only samples the LPDDR4 MR4 register when the
> Temperature Update Flag (TUF) field (MR4[7] ) is 1’b1. If the
> LPDDR4 memory is initialized and starts operation above 85 °C
> (MR4[2:0] > 3’b011), the MR4 Temperature Update Flag (TUF) will
> not be set. The DDR Controller will therefore not automatically
> adjust the memory refresh rate or de-rate memory timings based
> on the LPDDR4 memory temperature. This may cause the controller
> incorrectly setting the refresh period, potentially cause the
> LPDDR4 memory losing data contents and lead to possible data
> integrity issues above 85 °C.
>
> Errata provides three possible workaround options, while option 2
> is the most reasonable:
>
> Disable the automatic derating logic of the DDR controller and
> apply fixed x2 refresh rate (0.5x refresh). This option is
> suitable for designs that are expected to boot at or above 85 °C
> and memory’s MR4[2:0] (Refresh Rate) DOES NOT report the following
> conditions:
> 3b101: 0.25x refresh, no de-rating
> 3b110: 0.25x refresh, with de-rating
> 3b111: SDRAM High temperature operating limit exceeded
>
> [1]: https://www.nxp.com/docs/en/errata/IMX8MM_0N87W.pdf
>
> Signed-off-by: Andrejs Cainikovs
Acked-by: Marcel Ziswiler
> ---
> board/toradex/verdin-imx8mm/lpddr4_timing.c | 51 ++---
> 1 file changed, 24 insertions(+), 27 deletions(-)
>
> diff --git a/board/toradex/verdin-imx8mm/lpddr4_timing.c
> b/board/toradex/verdin-imx8mm/lpddr4_timing.c
> index d114abf9d67..4dfec679b11 100644
> --- a/board/toradex/verdin-imx8mm/lpddr4_timing.c
> +++ b/board/toradex/verdin-imx8mm/lpddr4_timing.c
> @@ -1,12 +1,11 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2020 Toradex
> + * Copyright 2023 Toradex
> *
> * Generated code from MX8M_DDR_tool
> - * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
> *
> - * DDR calibration created with mscale_ddr_tool_v210_setup.exe using
> - * MX8M_Mini_LPDDR4_RPA_v14 Verdin iMX8MM V1.0.xlsx as of 1. Nov. 2019.
> + * DDR calibration created with mscale_ddr_tool_v3.31_setup.exe using
> + * MX8M_Mini_LPDDR4_RPA_v22 Verdin iMX8MM V1.0.xlsx as of 7. Aug. 2023.
> */
>
> #include
> @@ -17,22 +16,22 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
> {0x3d400304, 0x1},
> {0x3d400030, 0x1},
> {0x3d40, 0xa1080020},
> - {0x3d400020, 0x203},
> + {0x3d400020, 0x202},
> {0x3d400024, 0x3a980},
> - {0x3d400064, 0x5b00d2},
> + {0x3d400064, 0x2d00d2},
> {0x3d4000d0, 0xc00305ba},
> {0x3d4000d4, 0x94},
> {0x3d4000dc, 0xd4002d},
> {0x3d4000e0, 0x31},
> {0x3d4000e8, 0x66004d},
> {0x3d4000ec, 0x16004d},
> - {0x3d400100, 0x191e1920},
> + {0x3d400100, 0x191e0c20},
> {0x3d400104, 0x60630},
> {0x3d40010c, 0xb0b000},
> {0x3d400110, 0xe04080e},
> {0x3d400114, 0x2040c0c},
> {0x3d400118, 0x1010007},
> - {0x3d40011c, 0x401},
> + {0x3d40011c, 0x402},
> {0x3d400130, 0x20600},
> {0x3d400134, 0xc12},
> {0x3d400138, 0xd8},
> @@ -49,7 +48,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
> {0x3d4001b0, 0x11},
> {0x3d4001c0, 0x1},
> {0x3d4001c4, 0x1},
> - {0x3d4000f4, 0xc99},
> + {0x3d4000f4, 0x699},
> {0x3d400108, 0x70e1617},
> {0x3d400200, 0x1f},
> {0x3d40020c, 0x0},
> @@ -57,6 +56,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
> {0x3d400204, 0x80808},
> {0x3d400214, 0x7070707},
> {0x3d400218, 0x7070707},
> + {0x3d40021c, 0xf0f},
> {0x3d400250, 0x29001701},
> {0x3d400254, 0x2c},
> {0x3d40025c, 0x430},
> @@ -68,22 +68,22 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
> {0x3d400498, 0x620096},
> {0x3d40049c, 0x1100e07},
> {0x3d4004a0, 0xc8012c},
> - {0x3d402020, 0x1},
> + {0x3d402020, 0x0},
> {0x3d402024, 0x7d00},
> {0x3d402050, 0x20d040},
> - {0x3d402064, 0xc001c},
> + {0x3d402064, 0x6001c},
> {0x3d4020dc, 0x84},
> {0x3d4020e0, 0x31},
> {0x3d4020e8, 0x66004d},
> {0x3d4020ec,
[PATCH v1] board: toradex: verdin-imx8mm: set fixed LPDDR4 refresh rate as per errata ERR050805
From: Andrejs Cainikovs
Update lpddr4 configuration and training using updated spreadsheet and
tools from NXP using data from previous spreadsheet and verified
toward datasheet:
- MX8M_Mini_LPDDR4_RPA_v22.xlsx
- mscale_ddr_tool_v3.31_setup.exe
The most relevant update is related to errata ERR050805:
"DRAM: Controller automatic derating logic may not work when
the LPDDR4 memory temperature is above 85 °C at initialization"
Other relevant fixes:
- DRAMTMG7 register: corrected calculation of T_CKPDX parameter
(equal to tCKCKEH for LPDDR4)
- RANKCTL register: corrected calculations for ODTLon and ODTLoff
to follow the JEDEC specification
- ADDRMAP7 register: added support for 17-row devices
As per errata ERR050805:
An issue exists with the automatic derating logic of the DDR
controller that only samples the LPDDR4 MR4 register when the
Temperature Update Flag (TUF) field (MR4[7] ) is 1’b1. If the
LPDDR4 memory is initialized and starts operation above 85 °C
(MR4[2:0] > 3’b011), the MR4 Temperature Update Flag (TUF) will
not be set. The DDR Controller will therefore not automatically
adjust the memory refresh rate or de-rate memory timings based
on the LPDDR4 memory temperature. This may cause the controller
incorrectly setting the refresh period, potentially cause the
LPDDR4 memory losing data contents and lead to possible data
integrity issues above 85 °C.
Errata provides three possible workaround options, while option 2
is the most reasonable:
Disable the automatic derating logic of the DDR controller and
apply fixed x2 refresh rate (0.5x refresh). This option is
suitable for designs that are expected to boot at or above 85 °C
and memory’s MR4[2:0] (Refresh Rate) DOES NOT report the following
conditions:
3b101: 0.25x refresh, no de-rating
3b110: 0.25x refresh, with de-rating
3b111: SDRAM High temperature operating limit exceeded
[1]: https://www.nxp.com/docs/en/errata/IMX8MM_0N87W.pdf
Signed-off-by: Andrejs Cainikovs
---
board/toradex/verdin-imx8mm/lpddr4_timing.c | 51 ++---
1 file changed, 24 insertions(+), 27 deletions(-)
diff --git a/board/toradex/verdin-imx8mm/lpddr4_timing.c
b/board/toradex/verdin-imx8mm/lpddr4_timing.c
index d114abf9d67..4dfec679b11 100644
--- a/board/toradex/verdin-imx8mm/lpddr4_timing.c
+++ b/board/toradex/verdin-imx8mm/lpddr4_timing.c
@@ -1,12 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2020 Toradex
+ * Copyright 2023 Toradex
*
* Generated code from MX8M_DDR_tool
- * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
*
- * DDR calibration created with mscale_ddr_tool_v210_setup.exe using
- * MX8M_Mini_LPDDR4_RPA_v14 Verdin iMX8MM V1.0.xlsx as of 1. Nov. 2019.
+ * DDR calibration created with mscale_ddr_tool_v3.31_setup.exe using
+ * MX8M_Mini_LPDDR4_RPA_v22 Verdin iMX8MM V1.0.xlsx as of 7. Aug. 2023.
*/
#include
@@ -17,22 +16,22 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d400304, 0x1},
{0x3d400030, 0x1},
{0x3d40, 0xa1080020},
- {0x3d400020, 0x203},
+ {0x3d400020, 0x202},
{0x3d400024, 0x3a980},
- {0x3d400064, 0x5b00d2},
+ {0x3d400064, 0x2d00d2},
{0x3d4000d0, 0xc00305ba},
{0x3d4000d4, 0x94},
{0x3d4000dc, 0xd4002d},
{0x3d4000e0, 0x31},
{0x3d4000e8, 0x66004d},
{0x3d4000ec, 0x16004d},
- {0x3d400100, 0x191e1920},
+ {0x3d400100, 0x191e0c20},
{0x3d400104, 0x60630},
{0x3d40010c, 0xb0b000},
{0x3d400110, 0xe04080e},
{0x3d400114, 0x2040c0c},
{0x3d400118, 0x1010007},
- {0x3d40011c, 0x401},
+ {0x3d40011c, 0x402},
{0x3d400130, 0x20600},
{0x3d400134, 0xc12},
{0x3d400138, 0xd8},
@@ -49,7 +48,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d4001b0, 0x11},
{0x3d4001c0, 0x1},
{0x3d4001c4, 0x1},
- {0x3d4000f4, 0xc99},
+ {0x3d4000f4, 0x699},
{0x3d400108, 0x70e1617},
{0x3d400200, 0x1f},
{0x3d40020c, 0x0},
@@ -57,6 +56,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d400204, 0x80808},
{0x3d400214, 0x7070707},
{0x3d400218, 0x7070707},
+ {0x3d40021c, 0xf0f},
{0x3d400250, 0x29001701},
{0x3d400254, 0x2c},
{0x3d40025c, 0x430},
@@ -68,22 +68,22 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d400498, 0x620096},
{0x3d40049c, 0x1100e07},
{0x3d4004a0, 0xc8012c},
- {0x3d402020, 0x1},
+ {0x3d402020, 0x0},
{0x3d402024, 0x7d00},
{0x3d402050, 0x20d040},
- {0x3d402064, 0xc001c},
+ {0x3d402064, 0x6001c},
{0x3d4020dc, 0x84},
{0x3d4020e0, 0x31},
{0x3d4020e8, 0x66004d},
{0x3d4020ec, 0x16004d},
- {0x3d402100, 0xa040305},
+ {0x3d402100, 0xa040105},
{0x3d402104, 0x30407},
{0x3d402108, 0x203060b},
{0x3d40210c, 0x505000},
{0x3d402110, 0x2040202},
{0x3d402114, 0x2030202},
