Re: [PATCH v1 06/17] clk: starfive: Add StarFive JH7110 clock driver
On 1/9/23 04:31, yanhong wang wrote:
On 2023/1/5 3:13, Sean Anderson wrote:
On 12/11/22 21:50, Yanhong Wang wrote:
+static const struct starfive_pllx_rate jh7110_pll2_tbl[] = {
+ PLLX_RATE(122880UL, 15, 768, 1, 1, 1),
+ PLLX_RATE(118800UL, 2, 99, 1, 1, 1),
+};
All of these rates set postdiv1/dacpd/dsmpd to 1. Do these fields need
to be stored?
The PLL supports integer and fraction muligple, you should set dacpd and dsmpd
to high while integer multiple mode,
and set both them to low while fraction multiple mode. The default configration
set to integer multiple mode.
Integer Multiple Mode
Both dacpd and dsmpd should be set as 1 while integer multiple mode.
The frequency of outputs can be figured out as below.
Fvco = Fref*Nl/M
NI is integer frequency dividing ratio of feedback divider, set by fbdiv1[11:0]
, NI = 8, 9, 10, 12.134095
M is frequency dividing ratio of pre-divider, set by prediv[5:0],M = 1,2...63
Fclko1 = Fvco/Q1
Q1 is frequency dividing ratio of post divider, set by postdiv1[1:0],Q1= 1,2,4,8
Fraction Multiple Mode
Both dacpd and dsmpd should be set as 0 while integer multiple mode.
Fvco = Fref*(NI+NE)/M
NI is integer frequency dividing ratio of feedback divider, set by fbdiv[11:0]
, NI = 8, 9, 10, 12.134095
NF is fractional frequency dividing ratio, set by frac[23:0], NF
=frac[23:0]/2^24= 0~0.9994
M is frequency dividing ratio of pre-divider, set by prediv[5:0],M = 1,2...63
Fclko1 = Fvco/Q1
Q1 is frequency dividing ratio of post divider, set by postdivl[1:0],Q1= 1,24,8
If you are going to set these to the same value every time you can omit them
from struct starfive_pllx_rate.
--Sean
Re: [PATCH v1 06/17] clk: starfive: Add StarFive JH7110 clock driver
On 2023/1/5 3:13, Sean Anderson wrote: > On 12/11/22 21:50, Yanhong Wang wrote: >> Add a DM clock driver for StarFive JH7110 SoC. > > > >> Signed-off-by: Yanhong Wang >> --- >> drivers/clk/Kconfig | 1 + >> drivers/clk/Makefile | 1 + >> drivers/clk/starfive/Kconfig | 15 + >> drivers/clk/starfive/Makefile | 4 + >> drivers/clk/starfive/clk-jh7110-pll.c | 362 ++ >> drivers/clk/starfive/clk-jh7110.c | 651 ++ >> drivers/clk/starfive/clk.h | 42 ++ >> 7 files changed, 1076 insertions(+) >> create mode 100644 drivers/clk/starfive/Kconfig >> create mode 100644 drivers/clk/starfive/Makefile >> create mode 100644 drivers/clk/starfive/clk-jh7110-pll.c >> create mode 100644 drivers/clk/starfive/clk-jh7110.c >> create mode 100644 drivers/clk/starfive/clk.h >> >> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig >> index 09aa97ee8c..4d60c84aad 100644 >> --- a/drivers/clk/Kconfig >> +++ b/drivers/clk/Kconfig >> @@ -235,6 +235,7 @@ source "drivers/clk/owl/Kconfig" >> source "drivers/clk/renesas/Kconfig" >> source "drivers/clk/sunxi/Kconfig" >> source "drivers/clk/sifive/Kconfig" >> +source "drivers/clk/starfive/Kconfig" >> source "drivers/clk/stm32/Kconfig" >> source "drivers/clk/tegra/Kconfig" >> source "drivers/clk/ti/Kconfig" >> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile >> index c274cda77c..66f5860356 100644 >> --- a/drivers/clk/Makefile >> +++ b/drivers/clk/Makefile >> @@ -13,6 +13,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += >> clk-composite.o >> obj-y += analogbits/ >> obj-y += imx/ >> +obj-$(CONFIG_CLK_JH7110) += starfive/ >> obj-y += tegra/ >> obj-y += ti/ >> obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/ >> diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig >> new file mode 100644 >> index 00..e4bf2a5c5e >> --- /dev/null >> +++ b/drivers/clk/starfive/Kconfig >> @@ -0,0 +1,15 @@ >> +# SPDX-License-Identifier: GPL-2.0+ >> + >> +config SPL_CLK_JH7110 >> + bool "SPL clock support for JH7110" >> + depends on STARFIVE_JH7110 && SPL >> + select SPL_CLK >> + select SPL_CLK_CCF >> + help >> + This enables SPL DM support for clock driver in JH7110. >> + >> +config CLK_JH7110 >> + bool "StarFive JH7110 clock support" >> + depends on CLK && CLK_CCF && STARFIVE_JH7110 >> + help >> + This enables support clock driver for StarFive JH7110 SoC platform. > > Not a huge fan of CCF drivers, but whatever works for you. > Thanks, i will fix. >> diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile >> new file mode 100644 >> index 00..ec0d157094 >> --- /dev/null >> +++ b/drivers/clk/starfive/Makefile >> @@ -0,0 +1,4 @@ >> +# SPDX-License-Identifier: GPL-2.0+ >> + >> +obj-y += clk-jh7110.o >> +obj-y += clk-jh7110-pll.o >> diff --git a/drivers/clk/starfive/clk-jh7110-pll.c >> b/drivers/clk/starfive/clk-jh7110-pll.c >> new file mode 100644 >> index 00..8be9500b62 >> --- /dev/null >> +++ b/drivers/clk/starfive/clk-jh7110-pll.c >> @@ -0,0 +1,362 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * Copyright (C) 2022 StarFive Technology Co., Ltd. >> + * >> + * Author: Yanhong Wang >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include "clk.h" >> + >> +#define UBOOT_DM_CLK_JH7110_PLLX "jh7110_clk_pllx" >> + >> +#define PLL0_DACPD_MASK BIT(24) >> +#define PLL0_DSMPD_MASK BIT(25) >> +#define PLL0_FBDIV_MASK GENMASK(11, 0) >> +#define PLL0_FRAC_MASK GENMASK(23, 0) >> +#define PLL0_PD_MASK BIT(27) >> +#define PLL0_POSTDIV1_MASK GENMASK(29, 28) >> +#define PLL0_PREDIV_MASK GENMASK(5, 0) >> +#define PLL1_DACPD_MASK BIT(15) >> +#define PLL1_DSMPD_MASK BIT(16) >> +#define PLL1_FBDIV_MASK GENMASK(28, 17) >> +#define PLL1_FRAC_MASK GENMASK(23, 0) >> +#define PLL1_PD_MASK BIT(27) >> +#define PLL1_POSTDIV1_MASK GENMASK(29, 28) >> +#define PLL1_PREDIV_MASK GENMASK(5, 0) >> +#define PLL2_DACPD_MASK BIT(15) >> +#define PLL2_DSMPD_MASK BIT(16) >> +#define PLL2_FBDIV_MASK GENMASK(28, 17) >> +#define PLL2_FRAC_MASK GENMASK(23, 0) >> +#define PLL2_PD_MASK BIT(27) >> +#define PLL2_POSTDIV1_MASK GENMASK(29, 28) >> +#define PLL2_PREDIV_MASK GENMASK(5, 0) >> + >> +#define PLL0_DACPD_OFFSET 0x18 >> +#define PLL0_DSMPD_OFFSET 0x18 >> +#define PLL0_FBDIV_OFFSET 0x1C >> +#define PLL0_FRAC_OFFSET 0x20 >> +#define PLL0_PD_OFFSET 0x20 >> +#define PLL0_POSTDIV1_OFFSET 0x20 >> +#define PLL0_PREDIV_OFFSET 0x24 >> +#define PLL1_DACPD_OFFSET 0x24 >> +#define PLL1_DSMPD_OFFSET 0x24 >> +#define PLL1_FBDIV_OFFSET 0x24 >> +#define PLL1_FRAC_OFFSET 0x28 >> +#define PLL1_PD_OFFSET 0x28 >> +#define PLL1_POSTDIV1_OFFSET 0x28 >> +#define PL
Re: [PATCH v1 06/17] clk: starfive: Add StarFive JH7110 clock driver
On 12/11/22 21:50, Yanhong Wang wrote: Add a DM clock driver for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/starfive/Kconfig | 15 + drivers/clk/starfive/Makefile | 4 + drivers/clk/starfive/clk-jh7110-pll.c | 362 ++ drivers/clk/starfive/clk-jh7110.c | 651 ++ drivers/clk/starfive/clk.h| 42 ++ 7 files changed, 1076 insertions(+) create mode 100644 drivers/clk/starfive/Kconfig create mode 100644 drivers/clk/starfive/Makefile create mode 100644 drivers/clk/starfive/clk-jh7110-pll.c create mode 100644 drivers/clk/starfive/clk-jh7110.c create mode 100644 drivers/clk/starfive/clk.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 09aa97ee8c..4d60c84aad 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -235,6 +235,7 @@ source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/sunxi/Kconfig" source "drivers/clk/sifive/Kconfig" +source "drivers/clk/starfive/Kconfig" source "drivers/clk/stm32/Kconfig" source "drivers/clk/tegra/Kconfig" source "drivers/clk/ti/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index c274cda77c..66f5860356 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o obj-y += analogbits/ obj-y += imx/ +obj-$(CONFIG_CLK_JH7110) += starfive/ obj-y += tegra/ obj-y += ti/ obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/ diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig new file mode 100644 index 00..e4bf2a5c5e --- /dev/null +++ b/drivers/clk/starfive/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0+ + +config SPL_CLK_JH7110 + bool "SPL clock support for JH7110" + depends on STARFIVE_JH7110 && SPL + select SPL_CLK + select SPL_CLK_CCF + help + This enables SPL DM support for clock driver in JH7110. + +config CLK_JH7110 + bool "StarFive JH7110 clock support" + depends on CLK && CLK_CCF && STARFIVE_JH7110 + help + This enables support clock driver for StarFive JH7110 SoC platform. Not a huge fan of CCF drivers, but whatever works for you. diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile new file mode 100644 index 00..ec0d157094 --- /dev/null +++ b/drivers/clk/starfive/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += clk-jh7110.o +obj-y += clk-jh7110-pll.o diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c new file mode 100644 index 00..8be9500b62 --- /dev/null +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * + * Author: Yanhong Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define UBOOT_DM_CLK_JH7110_PLLX "jh7110_clk_pllx" + +#define PLL0_DACPD_MASKBIT(24) +#define PLL0_DSMPD_MASKBIT(25) +#define PLL0_FBDIV_MASKGENMASK(11, 0) +#define PLL0_FRAC_MASK GENMASK(23, 0) +#define PLL0_PD_MASK BIT(27) +#define PLL0_POSTDIV1_MASK GENMASK(29, 28) +#define PLL0_PREDIV_MASK GENMASK(5, 0) +#define PLL1_DACPD_MASKBIT(15) +#define PLL1_DSMPD_MASKBIT(16) +#define PLL1_FBDIV_MASKGENMASK(28, 17) +#define PLL1_FRAC_MASK GENMASK(23, 0) +#define PLL1_PD_MASK BIT(27) +#define PLL1_POSTDIV1_MASK GENMASK(29, 28) +#define PLL1_PREDIV_MASK GENMASK(5, 0) +#define PLL2_DACPD_MASKBIT(15) +#define PLL2_DSMPD_MASKBIT(16) +#define PLL2_FBDIV_MASKGENMASK(28, 17) +#define PLL2_FRAC_MASK GENMASK(23, 0) +#define PLL2_PD_MASK BIT(27) +#define PLL2_POSTDIV1_MASK GENMASK(29, 28) +#define PLL2_PREDIV_MASK GENMASK(5, 0) + +#define PLL0_DACPD_OFFSET 0x18 +#define PLL0_DSMPD_OFFSET 0x18 +#define PLL0_FBDIV_OFFSET 0x1C +#define PLL0_FRAC_OFFSET 0x20 +#define PLL0_PD_OFFSET 0x20 +#define PLL0_POSTDIV1_OFFSET 0x20 +#define PLL0_PREDIV_OFFSET 0x24 +#define PLL1_DACPD_OFFSET 0x24 +#define PLL1_DSMPD_OFFSET 0x24 +#define PLL1_FBDIV_OFFSET 0x24 +#define PLL1_FRAC_OFFSET 0x28 +#define PLL1_PD_OFFSET 0x28 +#define PLL1_POSTDIV1_OFFSET 0x28 +#define PLL1_PREDIV_OFFSET 0x2c +#define PLL2_DACPD_OFFSET 0x2c +#define PLL2_DSMPD_OFFSET 0x2c +#define PLL2_FBDIV_OFFSET 0x2c +#define PLL2_FRAC_OFFSET 0x30 +#define PLL2_PD_OFFSET 0x30 +#define PLL2_POSTDIV1_OFFSET 0x30 +#define PLL2_PREDIV_OFFSET 0x34 + +#define PLL_PD_OFF 1 +#define PLL_PD_ON 0 + +#define CLK_D
[PATCH v1 06/17] clk: starfive: Add StarFive JH7110 clock driver
Add a DM clock driver for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/starfive/Kconfig | 15 + drivers/clk/starfive/Makefile | 4 + drivers/clk/starfive/clk-jh7110-pll.c | 362 ++ drivers/clk/starfive/clk-jh7110.c | 651 ++ drivers/clk/starfive/clk.h| 42 ++ 7 files changed, 1076 insertions(+) create mode 100644 drivers/clk/starfive/Kconfig create mode 100644 drivers/clk/starfive/Makefile create mode 100644 drivers/clk/starfive/clk-jh7110-pll.c create mode 100644 drivers/clk/starfive/clk-jh7110.c create mode 100644 drivers/clk/starfive/clk.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 09aa97ee8c..4d60c84aad 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -235,6 +235,7 @@ source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/sunxi/Kconfig" source "drivers/clk/sifive/Kconfig" +source "drivers/clk/starfive/Kconfig" source "drivers/clk/stm32/Kconfig" source "drivers/clk/tegra/Kconfig" source "drivers/clk/ti/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index c274cda77c..66f5860356 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o obj-y += analogbits/ obj-y += imx/ +obj-$(CONFIG_CLK_JH7110) += starfive/ obj-y += tegra/ obj-y += ti/ obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/ diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig new file mode 100644 index 00..e4bf2a5c5e --- /dev/null +++ b/drivers/clk/starfive/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0+ + +config SPL_CLK_JH7110 + bool "SPL clock support for JH7110" + depends on STARFIVE_JH7110 && SPL + select SPL_CLK + select SPL_CLK_CCF + help + This enables SPL DM support for clock driver in JH7110. + +config CLK_JH7110 + bool "StarFive JH7110 clock support" + depends on CLK && CLK_CCF && STARFIVE_JH7110 + help + This enables support clock driver for StarFive JH7110 SoC platform. diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile new file mode 100644 index 00..ec0d157094 --- /dev/null +++ b/drivers/clk/starfive/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += clk-jh7110.o +obj-y += clk-jh7110-pll.o diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c new file mode 100644 index 00..8be9500b62 --- /dev/null +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * + * Author: Yanhong Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define UBOOT_DM_CLK_JH7110_PLLX "jh7110_clk_pllx" + +#define PLL0_DACPD_MASKBIT(24) +#define PLL0_DSMPD_MASKBIT(25) +#define PLL0_FBDIV_MASKGENMASK(11, 0) +#define PLL0_FRAC_MASK GENMASK(23, 0) +#define PLL0_PD_MASK BIT(27) +#define PLL0_POSTDIV1_MASK GENMASK(29, 28) +#define PLL0_PREDIV_MASK GENMASK(5, 0) +#define PLL1_DACPD_MASKBIT(15) +#define PLL1_DSMPD_MASKBIT(16) +#define PLL1_FBDIV_MASKGENMASK(28, 17) +#define PLL1_FRAC_MASK GENMASK(23, 0) +#define PLL1_PD_MASK BIT(27) +#define PLL1_POSTDIV1_MASK GENMASK(29, 28) +#define PLL1_PREDIV_MASK GENMASK(5, 0) +#define PLL2_DACPD_MASKBIT(15) +#define PLL2_DSMPD_MASKBIT(16) +#define PLL2_FBDIV_MASKGENMASK(28, 17) +#define PLL2_FRAC_MASK GENMASK(23, 0) +#define PLL2_PD_MASK BIT(27) +#define PLL2_POSTDIV1_MASK GENMASK(29, 28) +#define PLL2_PREDIV_MASK GENMASK(5, 0) + +#define PLL0_DACPD_OFFSET 0x18 +#define PLL0_DSMPD_OFFSET 0x18 +#define PLL0_FBDIV_OFFSET 0x1C +#define PLL0_FRAC_OFFSET 0x20 +#define PLL0_PD_OFFSET 0x20 +#define PLL0_POSTDIV1_OFFSET 0x20 +#define PLL0_PREDIV_OFFSET 0x24 +#define PLL1_DACPD_OFFSET 0x24 +#define PLL1_DSMPD_OFFSET 0x24 +#define PLL1_FBDIV_OFFSET 0x24 +#define PLL1_FRAC_OFFSET 0x28 +#define PLL1_PD_OFFSET 0x28 +#define PLL1_POSTDIV1_OFFSET 0x28 +#define PLL1_PREDIV_OFFSET 0x2c +#define PLL2_DACPD_OFFSET 0x2c +#define PLL2_DSMPD_OFFSET 0x2c +#define PLL2_FBDIV_OFFSET 0x2c +#define PLL2_FRAC_OFFSET 0x30 +#define PLL2_PD_OFFSET 0x30 +#define PLL2_POSTDIV1_OFFSET 0x30 +#define PLL2_PREDIV_OFFSET 0x34 + +#define PLL_PD_OFF 1 +#define PLL_PD_ON 0 + +#define CLK_DDR_BUS_MASK GENMASK(29, 24) +#define CLK_DDR_BUS_OFFSET 0xAC +#define CLK_DDR_BUS_OSC_DIV2 0 +#define CLK_DDR_BUS_PLL1_DIV
