Re: [PATCH v1 1/5] riscv: dts: Split Microchip device tree
Hi Bin, On Mon, Nov 1, 2021 at 2:11 PM Bin Meng wrote: > Hi Padmarao, > > On Fri, Oct 22, 2021 at 4:58 PM Padmarao Begari > wrote: > > > > The device tree split into .dtsi and .dts files, common > > device node for eMMC/SD, enable I2C1, UART1 for console > > instead of UART0, enable the DDR 2GB memory and in > > that 288MB memory is reserved for fabric buffer. > > > > Signed-off-by: Padmarao Begari > > --- > > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 518 > > arch/riscv/dts/microchip-mpfs.dtsi| 571 ++ > > .../microchip-mpfs-plic.h | 195 ++ > > .../interrupt-controller/riscv-hart.h | 18 + > > 4 files changed, 913 insertions(+), 389 deletions(-) > > create mode 100644 arch/riscv/dts/microchip-mpfs.dtsi > > create mode 100644 > include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h > > create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h > > Are these files sync'ed from upstream Linux kernel? > > No, We are going to submit these files to the upstream Linux kernel very soon. Regards Padmarao > > > > [snip] > > Regards, > Bin >
Re: [PATCH v1 1/5] riscv: dts: Split Microchip device tree
Hi Padmarao, On Fri, Oct 22, 2021 at 4:58 PM Padmarao Begari wrote: > > The device tree split into .dtsi and .dts files, common > device node for eMMC/SD, enable I2C1, UART1 for console > instead of UART0, enable the DDR 2GB memory and in > that 288MB memory is reserved for fabric buffer. > > Signed-off-by: Padmarao Begari > --- > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 518 > arch/riscv/dts/microchip-mpfs.dtsi| 571 ++ > .../microchip-mpfs-plic.h | 195 ++ > .../interrupt-controller/riscv-hart.h | 18 + > 4 files changed, 913 insertions(+), 389 deletions(-) > create mode 100644 arch/riscv/dts/microchip-mpfs.dtsi > create mode 100644 > include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h > create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h Are these files sync'ed from upstream Linux kernel? > [snip] Regards, Bin
Re: [PATCH v1 1/5] riscv: dts: Split Microchip device tree
On Fri, Oct 22, 2021 at 02:26:44PM +0530, Padmarao Begari wrote: > The device tree split into .dtsi and .dts files, common > device node for eMMC/SD, enable I2C1, UART1 for console > instead of UART0, enable the DDR 2GB memory and in > that 288MB memory is reserved for fabric buffer. > > Signed-off-by: Padmarao Begari > --- > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 518 > arch/riscv/dts/microchip-mpfs.dtsi| 571 ++ > .../microchip-mpfs-plic.h | 195 ++ > .../interrupt-controller/riscv-hart.h | 18 + > 4 files changed, 913 insertions(+), 389 deletions(-) > create mode 100644 arch/riscv/dts/microchip-mpfs.dtsi > create mode 100644 > include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h > create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h Reviewed-by: Leo Yu-Chi Liang
[PATCH v1 1/5] riscv: dts: Split Microchip device tree
The device tree split into .dtsi and .dts files, common
device node for eMMC/SD, enable I2C1, UART1 for console
instead of UART0, enable the DDR 2GB memory and in
that 288MB memory is reserved for fabric buffer.
Signed-off-by: Padmarao Begari
---
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 518
arch/riscv/dts/microchip-mpfs.dtsi| 571 ++
.../microchip-mpfs-plic.h | 195 ++
.../interrupt-controller/riscv-hart.h | 18 +
4 files changed, 913 insertions(+), 389 deletions(-)
create mode 100644 arch/riscv/dts/microchip-mpfs.dtsi
create mode 100644
include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h
create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
index 89c4cf5fb2..287ef3d23b 100644
--- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
@@ -1,417 +1,157 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020 Microchip Technology Inc */
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Microchip Technology Inc.
+ * Padmarao Begari
+ */
/dts-v1/;
-#include "dt-bindings/clock/microchip-mpfs-clock.h"
+
+#include "microchip-mpfs.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ100
/ {
- #address-cells = <2>;
- #size-cells = <2>;
- model = "Microchip MPFS Icicle Kit";
- compatible = "microchip,mpfs-icicle-kit";
+ model = "Microchip PolarFire-SoC Icicle Kit";
+ compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
aliases {
- serial0 =
- ethernet0 =
+ serial1 =
+ ethernet0 =
};
chosen {
- stdout-path = "serial0";
+ stdout-path = "serial1";
};
- cpucomplex: cpus {
- #address-cells = <1>;
- #size-cells = <0>;
+ cpus {
timebase-frequency = ;
- cpu0: cpu@0 {
- clocks = < CLK_CPU>;
- compatible = "sifive,e51", "sifive,rocket0", "riscv";
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <128>;
- i-cache-size = <16384>;
- reg = <0>;
- riscv,isa = "rv64imac";
- status = "disabled";
- operating-points = <
- /* kHz uV */
- 60 110
- 30 95
- 15 75
- >;
- cpu0intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu1: cpu@1 {
- clocks = < CLK_CPU>;
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- reg = <1>;
- riscv,isa = "rv64imafdc";
- tlb-split;
- status = "okay";
- operating-points = <
- /* kHz uV */
- 60 110
- 30 95
- 15 75
- >;
- cpu1intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu2: cpu@2 {
- clocks = < CLK_CPU>;
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
-
