Re: [PATCH v1 3/8] dt-bindings: clock: Add indexes for reset signals

2020-10-19 Thread Padmarao Begari 
On Sat, Oct 17, 2020 at 3:11 PM Anup Patel  wrote:

> On Fri, Oct 16, 2020 at 7:54 PM  wrote:
> >
> > From: Padmarao Begari 
> >
> > Add indexes for reset and clock control signals within the system
> register
> > module of the Microchip PolarFire SoC.
>
> This patch should be squashed into your PATCH7.
>
> ok

Regards
Padmarao

> >
> > Signed-off-by: Padmarao Begari 
> > ---
> >  .../dt-bindings/clock/microchip,pfsoc-clock.h | 45 +++
> >  1 file changed, 45 insertions(+)
> >  create mode 100644 include/dt-bindings/clock/microchip,pfsoc-clock.h
> >
> > diff --git a/include/dt-bindings/clock/microchip,pfsoc-clock.h
> b/include/dt-bindings/clock/microchip,pfsoc-clock.h
> > new file mode 100644
> > index 00..527cff1a28
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/microchip,pfsoc-clock.h
> > @@ -0,0 +1,45 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (C) 2020 Microchip Technology Inc.
> > + * Padmarao Begari 
> > + */
> > +
> > +#ifndef _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_
> > +#define _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_
> > +
> > +#define CLK_CPU0
> > +#define CLK_AXI1
> > +#define CLK_AHB2
> > +
> > +#define CLK_ENVM   3
> > +#define CLK_MAC0   4
> > +#define CLK_MAC1   5
> > +#define CLK_MMC6
> > +#define CLK_TIMER  7
> > +#define CLK_MMUART08
> > +#define CLK_MMUART19
> > +#define CLK_MMUART210
> > +#define CLK_MMUART311
> > +#define CLK_MMUART412
> > +#define CLK_SPI0   13
> > +#define CLK_SPI1   14
> > +#define CLK_I2C0   15
> > +#define CLK_I2C1   16
> > +#define CLK_CAN0   17
> > +#define CLK_CAN1   18
> > +#define CLK_USB19
> > +#define CLK_RESERVED   20
> > +#define CLK_RTC21
> > +#define CLK_QSPI   22
> > +#define CLK_GPIO0  23
> > +#define CLK_GPIO1  24
> > +#define CLK_GPIO2  25
> > +#define CLK_DDRC   26
> > +#define CLK_FIC0   27
> > +#define CLK_FIC1   28
> > +#define CLK_FIC2   29
> > +#define CLK_FIC3   30
> > +#define CLK_ATHENA 31
> > +#define CLK_CFM32
> > +
> > +#endif /* _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_ */
> > --
> > 2.17.1
> >
>
> Regards,
> Anup
>

Re: [PATCH v1 3/8] dt-bindings: clock: Add indexes for reset signals

2020-10-17 Thread Anup Patel 
On Fri, Oct 16, 2020 at 7:54 PM  wrote:
>
> From: Padmarao Begari 
>
> Add indexes for reset and clock control signals within the system register
> module of the Microchip PolarFire SoC.

This patch should be squashed into your PATCH7.

>
> Signed-off-by: Padmarao Begari 
> ---
>  .../dt-bindings/clock/microchip,pfsoc-clock.h | 45 +++
>  1 file changed, 45 insertions(+)
>  create mode 100644 include/dt-bindings/clock/microchip,pfsoc-clock.h
>
> diff --git a/include/dt-bindings/clock/microchip,pfsoc-clock.h 
> b/include/dt-bindings/clock/microchip,pfsoc-clock.h
> new file mode 100644
> index 00..527cff1a28
> --- /dev/null
> +++ b/include/dt-bindings/clock/microchip,pfsoc-clock.h
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2020 Microchip Technology Inc.
> + * Padmarao Begari 
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_
> +#define _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_
> +
> +#define CLK_CPU0
> +#define CLK_AXI1
> +#define CLK_AHB2
> +
> +#define CLK_ENVM   3
> +#define CLK_MAC0   4
> +#define CLK_MAC1   5
> +#define CLK_MMC6
> +#define CLK_TIMER  7
> +#define CLK_MMUART08
> +#define CLK_MMUART19
> +#define CLK_MMUART210
> +#define CLK_MMUART311
> +#define CLK_MMUART412
> +#define CLK_SPI0   13
> +#define CLK_SPI1   14
> +#define CLK_I2C0   15
> +#define CLK_I2C1   16
> +#define CLK_CAN0   17
> +#define CLK_CAN1   18
> +#define CLK_USB19
> +#define CLK_RESERVED   20
> +#define CLK_RTC21
> +#define CLK_QSPI   22
> +#define CLK_GPIO0  23
> +#define CLK_GPIO1  24
> +#define CLK_GPIO2  25
> +#define CLK_DDRC   26
> +#define CLK_FIC0   27
> +#define CLK_FIC1   28
> +#define CLK_FIC2   29
> +#define CLK_FIC3   30
> +#define CLK_ATHENA 31
> +#define CLK_CFM32
> +
> +#endif /* _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_ */
> --
> 2.17.1
>

Regards,
Anup

[PATCH v1 3/8] dt-bindings: clock: Add indexes for reset signals

2020-10-16 Thread padmarao.begari 
From: Padmarao Begari 

Add indexes for reset and clock control signals within the system register
module of the Microchip PolarFire SoC.

Signed-off-by: Padmarao Begari 
---
 .../dt-bindings/clock/microchip,pfsoc-clock.h | 45 +++
 1 file changed, 45 insertions(+)
 create mode 100644 include/dt-bindings/clock/microchip,pfsoc-clock.h

diff --git a/include/dt-bindings/clock/microchip,pfsoc-clock.h 
b/include/dt-bindings/clock/microchip,pfsoc-clock.h
new file mode 100644
index 00..527cff1a28
--- /dev/null
+++ b/include/dt-bindings/clock/microchip,pfsoc-clock.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Microchip Technology Inc.
+ * Padmarao Begari 
+ */
+
+#ifndef _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_
+#define _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_
+
+#define CLK_CPU0
+#define CLK_AXI1
+#define CLK_AHB2
+
+#define CLK_ENVM   3
+#define CLK_MAC0   4
+#define CLK_MAC1   5
+#define CLK_MMC6
+#define CLK_TIMER  7
+#define CLK_MMUART08
+#define CLK_MMUART19
+#define CLK_MMUART210
+#define CLK_MMUART311
+#define CLK_MMUART412
+#define CLK_SPI0   13
+#define CLK_SPI1   14
+#define CLK_I2C0   15
+#define CLK_I2C1   16
+#define CLK_CAN0   17
+#define CLK_CAN1   18
+#define CLK_USB19
+#define CLK_RESERVED   20
+#define CLK_RTC21
+#define CLK_QSPI   22
+#define CLK_GPIO0  23
+#define CLK_GPIO1  24
+#define CLK_GPIO2  25
+#define CLK_DDRC   26
+#define CLK_FIC0   27
+#define CLK_FIC1   28
+#define CLK_FIC2   29
+#define CLK_FIC3   30
+#define CLK_ATHENA 31
+#define CLK_CFM32
+
+#endif /* _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_ */
-- 
2.17.1