Re: [PATCH v2] mmc: sdhci-cadence: Add support for Cadence sdmmc v6

2024-09-05 Thread Tom Rini
On Tue, Nov 28, 2023 at 02:38:30PM +0800, Kuan Lim Lee wrote:

> Cadence SDMMC v6 controller has a lot of changes on initialize
> compared to v4 controller. PHY is needed by v6 controller.
> 
> Signed-off-by: Kuan Lim Lee 
> Co-developed-by: Alex Soo 
> Signed-off-by: Wei Liang Lim 
> Reviewed-by: Jaehoon Chung 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2] mmc: sdhci-cadence: Add support for Cadence sdmmc v6

2024-01-17 Thread Jaehoon Chung
On 11/28/23 15:38, Kuan Lim Lee wrote:
> Cadence SDMMC v6 controller has a lot of changes on initialize
> compared to v4 controller. PHY is needed by v6 controller.
> 
> Signed-off-by: Kuan Lim Lee 
> Co-developed-by: Alex Soo 
> Signed-off-by: Wei Liang Lim 

Reviewed-by: Jaehoon Chung 

Best Regards,
Jaehoon Chung

> ---
> Changes in v2
> - Rename file sdhci-cadence6-phy.c to sdhci-cadence6.c
> - Remove CONFIG_MMC_SDHCI_CADENCE_V6
> - Rewrite code of v6 configuration part
> - Add sdhci_cdns6_phy_init() function
> ---
>  drivers/mmc/Makefile |   1 +
>  drivers/mmc/sdhci-cadence.c  |  63 ++--
>  drivers/mmc/sdhci-cadence.h  |  69 
>  drivers/mmc/sdhci-cadence6.c | 294 +++
>  4 files changed, 376 insertions(+), 51 deletions(-)
>  create mode 100644 drivers/mmc/sdhci-cadence.h
>  create mode 100644 drivers/mmc/sdhci-cadence6.c



[PATCH v2] mmc: sdhci-cadence: Add support for Cadence sdmmc v6

2023-11-27 Thread Kuan Lim Lee
Cadence SDMMC v6 controller has a lot of changes on initialize
compared to v4 controller. PHY is needed by v6 controller.

Signed-off-by: Kuan Lim Lee 
Co-developed-by: Alex Soo 
Signed-off-by: Wei Liang Lim 
---
Changes in v2
- Rename file sdhci-cadence6-phy.c to sdhci-cadence6.c
- Remove CONFIG_MMC_SDHCI_CADENCE_V6
- Rewrite code of v6 configuration part
- Add sdhci_cdns6_phy_init() function
---
 drivers/mmc/Makefile |   1 +
 drivers/mmc/sdhci-cadence.c  |  63 ++--
 drivers/mmc/sdhci-cadence.h  |  69 
 drivers/mmc/sdhci-cadence6.c | 294 +++
 4 files changed, 376 insertions(+), 51 deletions(-)
 create mode 100644 drivers/mmc/sdhci-cadence.h
 create mode 100644 drivers/mmc/sdhci-cadence6.c

diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 2c65c4765a..136f06600a 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_MMC_SDHCI_ATMEL) += atmel_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_BCM2835)+= bcm2835_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_BCMSTB) += bcmstb_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_CADENCE)+= sdhci-cadence.o
+obj-$(CONFIG_MMC_SDHCI_CADENCE)+= sdhci-cadence6.o
 obj-$(CONFIG_MMC_SDHCI_AM654)  += am654_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_IPROC)  += iproc_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_KONA)   += kona_sdhci.o
diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c
index 327a05ad11..a5533af045 100644
--- a/drivers/mmc/sdhci-cadence.c
+++ b/drivers/mmc/sdhci-cadence.c
@@ -17,56 +17,7 @@
 #include 
 #include 
 #include 
-
-/* HRS - Host Register Set (specific to Cadence) */
-#define SDHCI_CDNS_HRS04   0x10/* PHY access port */
-#define   SDHCI_CDNS_HRS04_ACK BIT(26)
-#define   SDHCI_CDNS_HRS04_RD  BIT(25)
-#define   SDHCI_CDNS_HRS04_WR  BIT(24)
-#define   SDHCI_CDNS_HRS04_RDATA   GENMASK(23, 16)
-#define   SDHCI_CDNS_HRS04_WDATA   GENMASK(15, 8)
-#define   SDHCI_CDNS_HRS04_ADDRGENMASK(5, 0)
-
-#define SDHCI_CDNS_HRS06   0x18/* eMMC control */
-#define   SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
-#define   SDHCI_CDNS_HRS06_TUNEGENMASK(13, 8)
-#define   SDHCI_CDNS_HRS06_MODEGENMASK(2, 0)
-#define   SDHCI_CDNS_HRS06_MODE_SD 0x0
-#define   SDHCI_CDNS_HRS06_MODE_MMC_SDR0x2
-#define   SDHCI_CDNS_HRS06_MODE_MMC_DDR0x3
-#define   SDHCI_CDNS_HRS06_MODE_MMC_HS200  0x4
-#define   SDHCI_CDNS_HRS06_MODE_MMC_HS400  0x5
-#define   SDHCI_CDNS_HRS06_MODE_MMC_HS400ES0x6
-
-/* SRS - Slot Register Set (SDHCI-compatible) */
-#define SDHCI_CDNS_SRS_BASE0x200
-
-/* PHY */
-#define SDHCI_CDNS_PHY_DLY_SD_HS   0x00
-#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT  0x01
-#define SDHCI_CDNS_PHY_DLY_UHS_SDR12   0x02
-#define SDHCI_CDNS_PHY_DLY_UHS_SDR25   0x03
-#define SDHCI_CDNS_PHY_DLY_UHS_SDR50   0x04
-#define SDHCI_CDNS_PHY_DLY_UHS_DDR50   0x05
-#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
-#define SDHCI_CDNS_PHY_DLY_EMMC_SDR0x07
-#define SDHCI_CDNS_PHY_DLY_EMMC_DDR0x08
-#define SDHCI_CDNS_PHY_DLY_SDCLK   0x0b
-#define SDHCI_CDNS_PHY_DLY_HSMMC   0x0c
-#define SDHCI_CDNS_PHY_DLY_STROBE  0x0d
-
-/*
- * The tuned val register is 6 bit-wide, but not the whole of the range is
- * available.  The range 0-42 seems to be available (then 43 wraps around to 0)
- * but I am not quite sure if it is official.  Use only 0 to 39 for safety.
- */
-#define SDHCI_CDNS_MAX_TUNING_LOOP 40
-
-struct sdhci_cdns_plat {
-   struct mmc_config cfg;
-   struct mmc mmc;
-   void __iomem *hrs_addr;
-};
+#include "sdhci-cadence.h"
 
 struct sdhci_cdns_phy_cfg {
const char *property;
@@ -163,6 +114,9 @@ static void sdhci_cdns_set_control_reg(struct sdhci_host 
*host)
tmp &= ~SDHCI_CDNS_HRS06_MODE;
tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06);
+
+   if (device_is_compatible(mmc->dev, "cdns,sd6hc"))
+   sdhci_cdns6_phy_adj(mmc->dev, plat, mode);
 }
 
 static const struct sdhci_ops sdhci_cdns_ops = {
@@ -176,6 +130,9 @@ static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat 
*plat,
u32 tmp;
int i, ret;
 
+   if (device_is_compatible(plat->mmc.dev, "cdns,sd6hc"))
+   return sdhci_cdns6_set_tune_val(plat, val);
+
if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
return -EINVAL;
 
@@ -282,7 +239,10 @@ static int sdhci_cdns_probe(struct udevice *dev)
if (ret)
return ret;
 
-   ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
+   if (device_is_compatible(dev, "cdns,sd6hc"))
+   ret = sdhci_cdns6_phy_init(dev, plat);
+   else
+   ret = sdhci_cdns_phy_init(plat, gd->fdt