Re: [PATCH v2] watchdog: versal: Add support for Xilinx window watchdog
po 23. 3. 2020 v 15:47 odesÃlatel Michal Simek napsal:
>
> From: Ashok Reddy Soma
>
> Add support for Xilinx window watchdog, which can be found on
> Versal platforms.
>
> Signed-off-by: Ashok Reddy Soma
> Signed-off-by: Michal Simek
> ---
>
> Changes in v2:
> - Reverse subject prefixes
> - Convert to regmap as was asked
> - Rename WWDT_XILINX to WDT_XILINX
>
> MAINTAINERS| 1 +
> drivers/watchdog/Kconfig | 9 ++
> drivers/watchdog/Makefile | 1 +
> drivers/watchdog/xilinx_wwdt.c | 179 +
> 4 files changed, 190 insertions(+)
> create mode 100644 drivers/watchdog/xilinx_wwdt.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 92dda40a85df..b14d83475d7c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -447,6 +447,7 @@ M: Michal Simek
> S: Maintained
> T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
> F: arch/arm/mach-versal/
> +F: drivers/watchdog/xilinx_wwdt.c
> N: (?
> ARM VERSATILE EXPRESS DRIVERS
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index cb4da2e3cf88..6cafd243e049 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -185,6 +185,15 @@ config XILINX_TB_WATCHDOG
> Select this to enable Xilinx Axi watchdog timer, which can be found
> on some
> Xilinx Microblaze Platforms.
>
> +config WDT_XILINX
> + bool "Xilinx window watchdog timer support"
> + depends on WDT && ARCH_VERSAL
> + select REGMAP
> + imply WATCHDOG
> + help
> + Select this to enable Xilinx window watchdog timer, which can be
> found on
> + Xilinx Versal Platforms.
> +
> config WDT_TANGIER
> bool "Intel Tangier watchdog timer support"
> depends on WDT && INTEL_MID
> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> index 87f92a43b14e..519bbd3a40fc 100644
> --- a/drivers/watchdog/Makefile
> +++ b/drivers/watchdog/Makefile
> @@ -30,3 +30,4 @@ obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
> obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
> obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
> obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o
> +obj-$(CONFIG_WDT_XILINX) += xilinx_wwdt.o
> diff --git a/drivers/watchdog/xilinx_wwdt.c b/drivers/watchdog/xilinx_wwdt.c
> new file mode 100644
> index ..d8a585a48306
> --- /dev/null
> +++ b/drivers/watchdog/xilinx_wwdt.c
> @@ -0,0 +1,179 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Xilinx window watchdog timer driver.
> + *
> + * Author(s): Michal Simek
> + * Ashok Reddy Soma
> + *
> + * Copyright (c) 2020, Xilinx Inc.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* Refresh Register Masks */
> +#define XWT_WWREF_GWRR_MASKBIT(0) /* Refresh and start new period */
> +
> +/* Generic Control/Status Register Masks */
> +#define XWT_WWCSR_GWEN_MASKBIT(0) /* Enable Bit */
> +
> +/* Register offsets for the Wdt device */
> +#define XWT_WWREF_OFFSET 0x1000 /* Refresh Register */
> +#define XWT_WWCSR_OFFSET 0x2000 /* Control/Status Register */
> +#define XWT_WWOFF_OFFSET 0x2008 /* Offset Register */
> +#define XWT_WWCMP0_OFFSET 0x2010 /* Compare Value Register0 */
> +#define XWT_WWCMP1_OFFSET 0x2014 /* Compare Value Register1 */
> +#define XWT_WWWRST_OFFSET 0x2FD0 /* Warm Reset Register */
> +
> +struct xlnx_wwdt_priv {
> + bool enable_once;
> + struct regmap *regs;
> + struct clk clk;
> +};
> +
> +struct xlnx_wwdt_platdata {
> + bool enable_once;
> +};
> +
> +static int xlnx_wwdt_reset(struct udevice *dev)
> +{
> + struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
> +
> + regmap_write(wdt->regs, XWT_WWREF_OFFSET, XWT_WWREF_GWRR_MASK);
> +
> + return 0;
> +}
> +
> +static int xlnx_wwdt_stop(struct udevice *dev)
> +{
> + u32 csr;
> + struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
> +
> + if (wdt->enable_once) {
> + dev_warn(dev, "Can't stop Xilinx watchdog.\n");
> + return -EBUSY;
> + }
> +
> + /* Disable the generic watchdog timer */
> + regmap_read(wdt->regs, XWT_WWCSR_OFFSET, );
> + csr &= ~(XWT_WWCSR_GWEN_MASK);
> + regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr);
> +
> + clk_disable(>clk);
> +
> + dev_dbg(dev, "Watchdog disabled!\n");
> +
> + return 0;
> +}
> +
> +static int xlnx_wwdt_start(struct udevice *dev, u64 timeout, ulong flags)
> +{
> + int ret;
> + u32 csr;
> + u64 count;
> + unsigned long clock_f;
> + struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
> +
> + clock_f = clk_get_rate(>clk);
> + if (IS_ERR_VALUE(clock_f)) {
> + dev_err(dev, "failed to get rate\n");
> + return clock_f;
> + }
> +
> + dev_dbg(dev, "%s: CLK %ld\n", __func__, clock_f);
> +
> + /* Calculate timeout count */
> +
Re: [PATCH v2] watchdog: versal: Add support for Xilinx window watchdog
On 23.03.20 15:47, Michal Simek wrote: From: Ashok Reddy Soma Add support for Xilinx window watchdog, which can be found on Versal platforms. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- Changes in v2: - Reverse subject prefixes - Convert to regmap as was asked - Rename WWDT_XILINX to WDT_XILINX Reviewed-by: Stefan Roese Thanks, Stefan
[PATCH v2] watchdog: versal: Add support for Xilinx window watchdog
From: Ashok Reddy Soma
Add support for Xilinx window watchdog, which can be found on
Versal platforms.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Michal Simek
---
Changes in v2:
- Reverse subject prefixes
- Convert to regmap as was asked
- Rename WWDT_XILINX to WDT_XILINX
MAINTAINERS| 1 +
drivers/watchdog/Kconfig | 9 ++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/xilinx_wwdt.c | 179 +
4 files changed, 190 insertions(+)
create mode 100644 drivers/watchdog/xilinx_wwdt.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 92dda40a85df..b14d83475d7c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -447,6 +447,7 @@ M: Michal Simek
S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-versal/
+F: drivers/watchdog/xilinx_wwdt.c
N: (?
+ * Ashok Reddy Soma
+ *
+ * Copyright (c) 2020, Xilinx Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Refresh Register Masks */
+#define XWT_WWREF_GWRR_MASKBIT(0) /* Refresh and start new period */
+
+/* Generic Control/Status Register Masks */
+#define XWT_WWCSR_GWEN_MASKBIT(0) /* Enable Bit */
+
+/* Register offsets for the Wdt device */
+#define XWT_WWREF_OFFSET 0x1000 /* Refresh Register */
+#define XWT_WWCSR_OFFSET 0x2000 /* Control/Status Register */
+#define XWT_WWOFF_OFFSET 0x2008 /* Offset Register */
+#define XWT_WWCMP0_OFFSET 0x2010 /* Compare Value Register0 */
+#define XWT_WWCMP1_OFFSET 0x2014 /* Compare Value Register1 */
+#define XWT_WWWRST_OFFSET 0x2FD0 /* Warm Reset Register */
+
+struct xlnx_wwdt_priv {
+ bool enable_once;
+ struct regmap *regs;
+ struct clk clk;
+};
+
+struct xlnx_wwdt_platdata {
+ bool enable_once;
+};
+
+static int xlnx_wwdt_reset(struct udevice *dev)
+{
+ struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
+
+ regmap_write(wdt->regs, XWT_WWREF_OFFSET, XWT_WWREF_GWRR_MASK);
+
+ return 0;
+}
+
+static int xlnx_wwdt_stop(struct udevice *dev)
+{
+ u32 csr;
+ struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
+
+ if (wdt->enable_once) {
+ dev_warn(dev, "Can't stop Xilinx watchdog.\n");
+ return -EBUSY;
+ }
+
+ /* Disable the generic watchdog timer */
+ regmap_read(wdt->regs, XWT_WWCSR_OFFSET, );
+ csr &= ~(XWT_WWCSR_GWEN_MASK);
+ regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr);
+
+ clk_disable(>clk);
+
+ dev_dbg(dev, "Watchdog disabled!\n");
+
+ return 0;
+}
+
+static int xlnx_wwdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ int ret;
+ u32 csr;
+ u64 count;
+ unsigned long clock_f;
+ struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
+
+ clock_f = clk_get_rate(>clk);
+ if (IS_ERR_VALUE(clock_f)) {
+ dev_err(dev, "failed to get rate\n");
+ return clock_f;
+ }
+
+ dev_dbg(dev, "%s: CLK %ld\n", __func__, clock_f);
+
+ /* Calculate timeout count */
+ count = timeout * clock_f;
+
+ /* clk_enable will return -ENOSYS when it is not implemented */
+ ret = clk_enable(>clk);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "failed to enable clock\n");
+ return ret;
+ }
+
+ /*
+* Timeout count is half as there are two windows
+* first window overflow is ignored (interrupt),
+* reset is only generated at second window overflow
+*/
+ count = count >> 1;
+
+ /* Disable the generic watchdog timer */
+ regmap_read(wdt->regs, XWT_WWCSR_OFFSET, );
+ csr &= ~(XWT_WWCSR_GWEN_MASK);
+ regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr);
+
+ /* Set compare and offset registers for generic watchdog timeout */
+ regmap_write(wdt->regs, XWT_WWCMP0_OFFSET, (u32)count);
+ regmap_write(wdt->regs, XWT_WWCMP1_OFFSET, 0);
+ regmap_write(wdt->regs, XWT_WWOFF_OFFSET, (u32)count);
+
+ /* Enable the generic watchdog timer */
+ regmap_read(wdt->regs, XWT_WWCSR_OFFSET, );
+ csr |= (XWT_WWCSR_GWEN_MASK);
+ regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr);
+
+ return 0;
+}
+
+static int xlnx_wwdt_probe(struct udevice *dev)
+{
+ int ret;
+ struct xlnx_wwdt_platdata *platdata = dev_get_platdata(dev);
+ struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
+
+ dev_dbg(dev, "%s: Probing wdt%u\n", __func__, dev->seq);
+
+ ret = regmap_init_mem(dev_ofnode(dev), >regs);
+ if (ret) {
+ dev_dbg(dev, "failed to get regbase of wwdt\n");
+ return ret;
+ }
+
+ wdt->enable_once = platdata->enable_once;
+
+ ret = clk_get_by_index(dev, 0, >clk);
+ if (ret < 0)
+ dev_err(dev, "failed to get clock\n");
+
+ return ret;
+}
+
+static int
