Re: [PATCH v2 1/3] arm: dts: arria10: Move uboot specific properties to u-boot.dtsi
On Tue, Apr 7, 2020 at 9:43 AM Ley Foon Tan wrote:
>
> Move Uboot specific properties to *u-boot.dtsi files.
> Preparation to sync Arria 10 device tree from Linux.
>
> Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
> ---
> arch/arm/dts/socfpga_arria10-u-boot.dtsi | 123 ++
> arch/arm/dts/socfpga_arria10.dtsi | 28
> .../arm/dts/socfpga_arria10_socdk-u-boot.dtsi | 17 +++
> arch/arm/dts/socfpga_arria10_socdk.dtsi | 27
> .../socfpga_arria10_socdk_sdmmc-u-boot.dtsi | 46 +++
> arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 37 --
> 6 files changed, 186 insertions(+), 92 deletions(-)
> create mode 100644 arch/arm/dts/socfpga_arria10-u-boot.dtsi
> create mode 100644 arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
> create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
>
> diff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> new file mode 100644
> index ..c637b100738a
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> @@ -0,0 +1,123 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2014, 2020, Intel Corporation
> + */
> +
> +/ {
> + chosen {
> + tick-timer =
> + u-boot,dm-pre-reloc;
> + };
> +
> + memory@0 {
> + u-boot,dm-pre-reloc;
> + };
> +
> + soc {
> + u-boot,dm-pre-reloc;
> + };
> +};
> +
> + {
> + u-boot,dm-pre-reloc;
> +
> + clocks {
> + u-boot,dm-pre-reloc;
> + };
> +};
> +
> +_intosc_hs_div2_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +_intosc_ls_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +_free_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> + {
> + reset-names = "i2c";
> +};
> +
> + {
> + reset-names = "i2c";
> +};
> +
> + {
> + reset-names = "i2c";
> +};
> +
> + {
> + reset-names = "i2c";
> +};
> +
> + {
> + reset-names = "i2c";
> +};
> +
> +_mp_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +_sp_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +_sys_free_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +_periph_ref_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +_pll {
> + u-boot,dm-pre-reloc;
> +};
> +
> +_noc_base_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +_free_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> + {
> + u-boot,dm-pre-reloc;
> +};
> +
> +_noc_base_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +_pll {
> + u-boot,dm-pre-reloc;
> +};
> +
> + {
> + bank-name = "porta";
> +};
> +
> + {
> + bank-name = "portb";
> +};
> +
> + {
> + bank-name = "portc";
> +};
> +
> + {
> + u-boot,dm-pre-reloc;
> +};
> +
> + {
> + u-boot,dm-pre-reloc;
> +};
> +
> + {
> + u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/dts/socfpga_arria10.dtsi
> b/arch/arm/dts/socfpga_arria10.dtsi
> index cc529bcd1156..c8cd5a84b8a8 100644
> --- a/arch/arm/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/dts/socfpga_arria10.dtsi
> @@ -21,11 +21,6 @@
> #address-cells = <1>;
> #size-cells = <1>;
>
> - chosen {
> - tick-timer =
> - u-boot,dm-pre-reloc;
> - };
> -
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -60,7 +55,6 @@
> device_type = "soc";
> interrupt-parent = <>;
> ranges;
> - u-boot,dm-pre-reloc;
>
> amba {
> compatible = "simple-bus";
> @@ -99,35 +93,29 @@
> clkmgr: clkmgr@ffd04000 {
> compatible = "altr,clk-mgr";
> reg = <0xffd04000 0x1000>;
> - u-boot,dm-pre-reloc;
>
> clocks {
> #address-cells = <1>;
> #size-cells = <0>;
> - u-boot,dm-pre-reloc;
>
> cb_intosc_hs_div2_clk:
> cb_intosc_hs_div2_clk {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> - u-boot,dm-pre-reloc;
> };
>
> cb_intosc_ls_clk: cb_intosc_ls_clk {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> - u-boot,dm-pre-reloc;
> };
>
> f2s_free_clk: f2s_free_clk {
> #clock-cells = <0>;
>
[PATCH v2 1/3] arm: dts: arria10: Move uboot specific properties to u-boot.dtsi
Move Uboot specific properties to *u-boot.dtsi files.
Preparation to sync Arria 10 device tree from Linux.
Signed-off-by: Ley Foon Tan
---
arch/arm/dts/socfpga_arria10-u-boot.dtsi | 123 ++
arch/arm/dts/socfpga_arria10.dtsi | 28
.../arm/dts/socfpga_arria10_socdk-u-boot.dtsi | 17 +++
arch/arm/dts/socfpga_arria10_socdk.dtsi | 27
.../socfpga_arria10_socdk_sdmmc-u-boot.dtsi | 46 +++
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 37 --
6 files changed, 186 insertions(+), 92 deletions(-)
create mode 100644 arch/arm/dts/socfpga_arria10-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
diff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi
b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
new file mode 100644
index ..c637b100738a
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014, 2020, Intel Corporation
+ */
+
+/ {
+ chosen {
+ tick-timer =
+ u-boot,dm-pre-reloc;
+ };
+
+ memory@0 {
+ u-boot,dm-pre-reloc;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+ {
+ u-boot,dm-pre-reloc;
+
+ clocks {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+_intosc_hs_div2_clk {
+ u-boot,dm-pre-reloc;
+};
+
+_intosc_ls_clk {
+ u-boot,dm-pre-reloc;
+};
+
+_free_clk {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ reset-names = "i2c";
+};
+
+ {
+ reset-names = "i2c";
+};
+
+ {
+ reset-names = "i2c";
+};
+
+ {
+ reset-names = "i2c";
+};
+
+ {
+ reset-names = "i2c";
+};
+
+_mp_clk {
+ u-boot,dm-pre-reloc;
+};
+
+_sp_clk {
+ u-boot,dm-pre-reloc;
+};
+
+_sys_free_clk {
+ u-boot,dm-pre-reloc;
+};
+
+_periph_ref_clk {
+ u-boot,dm-pre-reloc;
+};
+
+_pll {
+ u-boot,dm-pre-reloc;
+};
+
+_noc_base_clk {
+ u-boot,dm-pre-reloc;
+};
+
+_free_clk {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+_noc_base_clk {
+ u-boot,dm-pre-reloc;
+};
+
+_pll {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ bank-name = "porta";
+};
+
+ {
+ bank-name = "portb";
+};
+
+ {
+ bank-name = "portc";
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_arria10.dtsi
b/arch/arm/dts/socfpga_arria10.dtsi
index cc529bcd1156..c8cd5a84b8a8 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -21,11 +21,6 @@
#address-cells = <1>;
#size-cells = <1>;
- chosen {
- tick-timer =
- u-boot,dm-pre-reloc;
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -60,7 +55,6 @@
device_type = "soc";
interrupt-parent = <>;
ranges;
- u-boot,dm-pre-reloc;
amba {
compatible = "simple-bus";
@@ -99,35 +93,29 @@
clkmgr: clkmgr@ffd04000 {
compatible = "altr,clk-mgr";
reg = <0xffd04000 0x1000>;
- u-boot,dm-pre-reloc;
clocks {
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
cb_intosc_hs_div2_clk:
cb_intosc_hs_div2_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
- u-boot,dm-pre-reloc;
};
cb_intosc_ls_clk: cb_intosc_ls_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
- u-boot,dm-pre-reloc;
};
f2s_free_clk: f2s_free_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
- u-boot,dm-pre-reloc;
};
osc1: osc1 {
#clock-cells = <0>;
compatible = "fixed-clock";
- u-boot,dm-pre-reloc;
};
