Re: [PATCH v2 1/3] arm: dts: imx8mm: Sync with linux-next 20231019
On Thu, Oct 19, 2023 at 9:06 AM Fabio Estevam wrote: > > From: Fabio Estevam > > Sync imx8mm.dtsi with linux-next 20231019. > > The motivation for doing this sync was a bug when doing "ums 0 mmc 1" > on imx8mm-evk. It worked well for the first time, but after doing > a CTRL+C and launching the ums again, the command did not work. > > Adam Ford suggested to sync imx8mm.dtsi with the Linux dts, as there was > a recent USB power domain reorganization there. > > After syncing the imx8mm.dtsi with Linux, the ums command works without > problem after a CTRL+C. > > Suggested-by: Adam Ford > Signed-off-by: Fabio Estevam Applied all to u-boot-imx next, thanks.
Re: [PATCH v2 1/3] arm: dts: imx8mm: Sync with linux-next 20231019
On Thu, Oct 19, 2023 at 5:06 AM Fabio Estevam wrote:
>
> From: Fabio Estevam
>
> Sync imx8mm.dtsi with linux-next 20231019.
>
> The motivation for doing this sync was a bug when doing "ums 0 mmc 1"
> on imx8mm-evk. It worked well for the first time, but after doing
> a CTRL+C and launching the ums again, the command did not work.
>
> Adam Ford suggested to sync imx8mm.dtsi with the Linux dts, as there was
> a recent USB power domain reorganization there.
>
> After syncing the imx8mm.dtsi with Linux, the ums command works without
> problem after a CTRL+C.
>
> Suggested-by: Adam Ford
> Signed-off-by: Fabio Estevam
> ---
> Changes since v1:
> - Rebased against latest U-Boot and synced with linux-next 20231019.
>
> arch/arm/dts/imx8mm.dtsi | 153 +--
> 1 file changed, 129 insertions(+), 24 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
> index afb90f59c83c..738024baaa57 100644
> --- a/arch/arm/dts/imx8mm.dtsi
> +++ b/arch/arm/dts/imx8mm.dtsi
> @@ -139,6 +139,7 @@
> A53_L2: l2-cache0 {
> compatible = "cache";
> cache-level = <2>;
> + cache-unified;
> cache-size = <0x8>;
> cache-line-size = <64>;
> cache-sets = <512>;
> @@ -276,6 +277,7 @@
> assigned-clocks = < IMX8MM_CLK_USB_PHY_REF>;
> assigned-clock-parents = < IMX8MM_SYS_PLL1_100M>;
> clock-names = "main_clk";
> + power-domains = <_otg1>;
> };
>
> usbphynop2: usbphynop2 {
> @@ -285,6 +287,7 @@
> assigned-clocks = < IMX8MM_CLK_USB_PHY_REF>;
> assigned-clock-parents = < IMX8MM_SYS_PLL1_100M>;
> clock-names = "main_clk";
> + power-domains = <_otg2>;
> };
>
> soc: soc@0 {
> @@ -396,6 +399,7 @@
> "pll8k", "pll11k",
> "clkext3";
> dmas = < 24 25 0x8000>;
> dma-names = "rx";
> + #sound-dai-cells = <0>;
> status = "disabled";
> };
>
> @@ -493,6 +497,8 @@
> compatible = "fsl,imx8mm-tmu";
> reg = <0x3026 0x1>;
> clocks = < IMX8MM_CLK_TMU_ROOT>;
> + nvmem-cells = <_calib>;
> + nvmem-cell-names = "calib";
> #thermal-sensor-cells = <0>;
> };
>
> @@ -547,8 +553,8 @@
> reg = <0x3033 0x1>;
> };
>
> - gpr: iomuxc-gpr@3034 {
> - compatible = "fsl,imx8mm-iomuxc-gpr",
> "fsl,imx6q-iomuxc-gpr", "syscon";
> + gpr: syscon@3034 {
> + compatible = "fsl,imx8mm-iomuxc-gpr",
> "syscon";
> reg = <0x3034 0x1>;
> };
>
> @@ -560,22 +566,40 @@
> #address-cells = <1>;
> #size-cells = <1>;
>
> - imx8mm_uid: unique-id@410 {
> + /*
> +* The register address below maps to the MX8M
> +* Fusemap Description Table entries this way.
> +* Assuming
> +* reg = ;
> +* then
> +* Fuse Address = (ADDR * 4) + 0x400
> +* Note that if SIZE is greater than 4, then
> +* each subsequent fuse is located at offset
> +* +0x10 in Fusemap Description Table (e.g.
> +* reg = <0x4 0x8> describes fuses 0x410 and
> +* 0x420).
> +*/
> + imx8mm_uid: unique-id@4 { /* 0x410-0x420 */
> reg = <0x4 0x8>;
> };
>
> - cpu_speed_grade: speed-grade@10 {
> + cpu_speed_grade: speed-grade@10 { /* 0x440 */
> reg = <0x10 4>;
> };
>
> - fec_mac_address: mac-address@90 {
> + tmu_calib: calib@3c { /* 0x4f0 */
> + reg = <0x3c 4>;
> + };
> +
> + fec_mac_address:
[PATCH v2 1/3] arm: dts: imx8mm: Sync with linux-next 20231019
From: Fabio Estevam
Sync imx8mm.dtsi with linux-next 20231019.
The motivation for doing this sync was a bug when doing "ums 0 mmc 1"
on imx8mm-evk. It worked well for the first time, but after doing
a CTRL+C and launching the ums again, the command did not work.
Adam Ford suggested to sync imx8mm.dtsi with the Linux dts, as there was
a recent USB power domain reorganization there.
After syncing the imx8mm.dtsi with Linux, the ums command works without
problem after a CTRL+C.
Suggested-by: Adam Ford
Signed-off-by: Fabio Estevam
---
Changes since v1:
- Rebased against latest U-Boot and synced with linux-next 20231019.
arch/arm/dts/imx8mm.dtsi | 153 +--
1 file changed, 129 insertions(+), 24 deletions(-)
diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
index afb90f59c83c..738024baaa57 100644
--- a/arch/arm/dts/imx8mm.dtsi
+++ b/arch/arm/dts/imx8mm.dtsi
@@ -139,6 +139,7 @@
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x8>;
cache-line-size = <64>;
cache-sets = <512>;
@@ -276,6 +277,7 @@
assigned-clocks = < IMX8MM_CLK_USB_PHY_REF>;
assigned-clock-parents = < IMX8MM_SYS_PLL1_100M>;
clock-names = "main_clk";
+ power-domains = <_otg1>;
};
usbphynop2: usbphynop2 {
@@ -285,6 +287,7 @@
assigned-clocks = < IMX8MM_CLK_USB_PHY_REF>;
assigned-clock-parents = < IMX8MM_SYS_PLL1_100M>;
clock-names = "main_clk";
+ power-domains = <_otg2>;
};
soc: soc@0 {
@@ -396,6 +399,7 @@
"pll8k", "pll11k",
"clkext3";
dmas = < 24 25 0x8000>;
dma-names = "rx";
+ #sound-dai-cells = <0>;
status = "disabled";
};
@@ -493,6 +497,8 @@
compatible = "fsl,imx8mm-tmu";
reg = <0x3026 0x1>;
clocks = < IMX8MM_CLK_TMU_ROOT>;
+ nvmem-cells = <_calib>;
+ nvmem-cell-names = "calib";
#thermal-sensor-cells = <0>;
};
@@ -547,8 +553,8 @@
reg = <0x3033 0x1>;
};
- gpr: iomuxc-gpr@3034 {
- compatible = "fsl,imx8mm-iomuxc-gpr",
"fsl,imx6q-iomuxc-gpr", "syscon";
+ gpr: syscon@3034 {
+ compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
reg = <0x3034 0x1>;
};
@@ -560,22 +566,40 @@
#address-cells = <1>;
#size-cells = <1>;
- imx8mm_uid: unique-id@410 {
+ /*
+* The register address below maps to the MX8M
+* Fusemap Description Table entries this way.
+* Assuming
+* reg = ;
+* then
+* Fuse Address = (ADDR * 4) + 0x400
+* Note that if SIZE is greater than 4, then
+* each subsequent fuse is located at offset
+* +0x10 in Fusemap Description Table (e.g.
+* reg = <0x4 0x8> describes fuses 0x410 and
+* 0x420).
+*/
+ imx8mm_uid: unique-id@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
- cpu_speed_grade: speed-grade@10 {
+ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
- fec_mac_address: mac-address@90 {
+ tmu_calib: calib@3c { /* 0x4f0 */
+ reg = <0x3c 4>;
+ };
+
+ fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
- anatop: anatop@3036 {
- compatible = "fsl,imx8mm-anatop",
