Re: [PATCH v2 2/7] arm: dts: rockchip: rk3288: partial sync grf and pmu nodes
On 2023/3/16 02:33, Johan Jonker wrote:
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the grf and pmu nodes.
Signed-off-by: Johan Jonker
Reviewed-by: Simon Glass
Tested-by: Simon Glass # chromebook-jerry
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3288.dtsi | 269 +--
1 file changed, 173 insertions(+), 96 deletions(-)
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 9cfb86f9..f06d1f5b 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include
#include
@@ -7,13 +7,16 @@
#include
#include
#include
-#include
-#include "skeleton.dtsi"
+#include
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
compatible = "rockchip,rk3288";
interrupt-parent = <&gic>;
+
aliases {
ethernet0 = &gmac;
i2c0 = &i2c0;
@@ -732,8 +735,128 @@
};
pmu: power-management@ff73 {
- compatible = "rockchip,rk3288-pmu", "syscon";
+ compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
reg = <0xff73 0x100>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3288-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ assigned-clocks = <&cru SCLK_EDP_24M>;
+ assigned-clock-parents = <&xin24m>;
+
+ /*
+* Note: Although SCLK_* are the working clocks
+* of device without including on the NOC, needed for
+* synchronous reset.
+*
+* The clocks on the which NOC:
+* ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
+* ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
+* ACLK_RGA is on ACLK_RGA_NIU.
+* The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
+*
+* Which clock are device clocks:
+* clocks devices
+* *_IEP IEP:Image Enhancement Processor
+* *_ISP ISP:Image Signal Processing
+* *_VIP VIP:Video Input Processor
+* *_VOP* VOP:Visual Output Processor
+* *_RGA RGA
+* *_EDP* EDP
+* *_LVDS_*LVDS
+* *_HDMI HDMI
+* *_MIPI_*MIPI
+*/
+ power-domain@RK3288_PD_VIO {
+ reg = ;
+ clocks = <&cru ACLK_IEP>,
+<&cru ACLK_ISP>,
+<&cru ACLK_RGA>,
+<&cru ACLK_VIP>,
+<&cru ACLK_VOP0>,
+<&cru ACLK_VOP1>,
+<&cru DCLK_VOP0>,
+<&cru DCLK_VOP1>,
+<&cru HCLK_IEP>,
+<&cru HCLK_ISP>,
+<&cru HCLK_RGA>,
+<&cru HCLK_VIP>,
+<&cru HCLK_VOP0>,
+<&cru HCLK_VOP1>,
+<&cru PCLK_EDP_CTRL>,
+<&cru PCLK_HDMI_CTRL>,
+<&cru PCLK_LVDS_PHY>,
+<&cru PCLK_MIPI_CSI>,
+<&cru PCLK_MIPI_DSI0>,
+<&cru PCLK_MIPI_DSI1>,
+<&cru SCLK_EDP_24M>,
+<&cru SCLK_EDP>,
+<&cru SCLK_ISP_JPE>,
+<&cru SCLK_ISP>,
+<&cru SCLK_RGA>;
+ pm_qos = <&qos_vio0_iep>,
+<&qos_vio1_vop>,
+<&qos_vio1_isp_w0>,
+<&qos_vio1_isp_w1>,
+<&qos_vio0_vop>,
+<&qos_vio0_vip>,
+
[PATCH v2 2/7] arm: dts: rockchip: rk3288: partial sync grf and pmu nodes
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the grf and pmu nodes.
Signed-off-by: Johan Jonker
Reviewed-by: Simon Glass
Tested-by: Simon Glass # chromebook-jerry
---
arch/arm/dts/rk3288.dtsi | 269 +--
1 file changed, 173 insertions(+), 96 deletions(-)
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 9cfb86f9..f06d1f5b 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include
#include
@@ -7,13 +7,16 @@
#include
#include
#include
-#include
-#include "skeleton.dtsi"
+#include
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
compatible = "rockchip,rk3288";
interrupt-parent = <&gic>;
+
aliases {
ethernet0 = &gmac;
i2c0 = &i2c0;
@@ -732,8 +735,128 @@
};
pmu: power-management@ff73 {
- compatible = "rockchip,rk3288-pmu", "syscon";
+ compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
reg = <0xff73 0x100>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3288-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ assigned-clocks = <&cru SCLK_EDP_24M>;
+ assigned-clock-parents = <&xin24m>;
+
+ /*
+* Note: Although SCLK_* are the working clocks
+* of device without including on the NOC, needed for
+* synchronous reset.
+*
+* The clocks on the which NOC:
+* ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
+* ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
+* ACLK_RGA is on ACLK_RGA_NIU.
+* The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
+*
+* Which clock are device clocks:
+* clocks devices
+* *_IEP IEP:Image Enhancement Processor
+* *_ISP ISP:Image Signal Processing
+* *_VIP VIP:Video Input Processor
+* *_VOP* VOP:Visual Output Processor
+* *_RGA RGA
+* *_EDP* EDP
+* *_LVDS_*LVDS
+* *_HDMI HDMI
+* *_MIPI_*MIPI
+*/
+ power-domain@RK3288_PD_VIO {
+ reg = ;
+ clocks = <&cru ACLK_IEP>,
+<&cru ACLK_ISP>,
+<&cru ACLK_RGA>,
+<&cru ACLK_VIP>,
+<&cru ACLK_VOP0>,
+<&cru ACLK_VOP1>,
+<&cru DCLK_VOP0>,
+<&cru DCLK_VOP1>,
+<&cru HCLK_IEP>,
+<&cru HCLK_ISP>,
+<&cru HCLK_RGA>,
+<&cru HCLK_VIP>,
+<&cru HCLK_VOP0>,
+<&cru HCLK_VOP1>,
+<&cru PCLK_EDP_CTRL>,
+<&cru PCLK_HDMI_CTRL>,
+<&cru PCLK_LVDS_PHY>,
+<&cru PCLK_MIPI_CSI>,
+<&cru PCLK_MIPI_DSI0>,
+<&cru PCLK_MIPI_DSI1>,
+<&cru SCLK_EDP_24M>,
+<&cru SCLK_EDP>,
+<&cru SCLK_ISP_JPE>,
+<&cru SCLK_ISP>,
+<&cru SCLK_RGA>;
+ pm_qos = <&qos_vio0_iep>,
+<&qos_vio1_vop>,
+<&qos_vio1_isp_w0>,
+<&qos_vio1_isp_w1>,
+<&qos_vio0_vop>,
+<&qos_vio0_vip>,
+<&qos_vio2_rga_r>,
+<&qos_vio2_rga_w>,
+
