[PATCH v2 3/4] arm64: dts: imx8mp: Add FEC RMII pin mux on i.MX8MP DHCOM

[sbabic]

> The i.MX8MP DHCOM SoM may come with either external RGMII PHY or
> LAN8740Ai RMII PHY on the SoM attached to FEC MAC. Add pin mux
> settings for both options, so that DT overlay can override these
> settings on SoM variant with the LAN8740Ai PHY.
> Signed-off-by: Marek Vasut 
Applied to u-boot-imx, next, thanks !

Best regards,
Stefano Babic

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[PATCH v2 3/4] arm64: dts: imx8mp: Add FEC RMII pin mux on i.MX8MP DHCOM

[Marek Vasut]

The i.MX8MP DHCOM SoM may come with either external RGMII PHY or
LAN8740Ai RMII PHY on the SoM attached to FEC MAC. Add pin mux
settings for both options, so that DT overlay can override these
settings on SoM variant with the LAN8740Ai PHY.

Signed-off-by: Marek Vasut 
---
Cc: "NXP i.MX U-Boot Team" 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Stefano Babic 
Cc: u-boot@lists.denx.de
---
V2: No change
---
 arch/arm/dts/imx8mp-dhcom-pdk2.dts |  2 ++
 arch/arm/dts/imx8mp-dhcom-som.dtsi | 22 +++---
 2 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2.dts 
b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
index 382fbedaf6b..ac104cd3e62 100644
--- a/arch/arm/dts/imx8mp-dhcom-pdk2.dts
+++ b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
@@ -117,7 +117,9 @@
 /delete-node/ 
 
  { /* Second ethernet */
+   pinctrl-0 = <_fec_rgmii>;
phy-handle = <>;
+   phy-mode = "rgmii";
 
mdio {
ethphypdk: ethernet-phy@7 { /* KSZ 9021 */
diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi 
b/arch/arm/dts/imx8mp-dhcom-som.dtsi
index b56607dfb39..9fd8bce8065 100644
--- a/arch/arm/dts/imx8mp-dhcom-som.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi
@@ -129,9 +129,9 @@
 
  { /* Second ethernet */
pinctrl-names = "default";
-   pinctrl-0 = <_fec>;
+   pinctrl-0 = <_fec_rmii>;
phy-handle = <>;
-   phy-mode = "rgmii";
+   phy-mode = "rmii";
fsl,magic-packet;
status = "okay";
 
@@ -723,7 +723,7 @@
>;
};
 
-   pinctrl_fec: dhcom-fec-grp {
+   pinctrl_fec_rgmii: dhcom-fec-rgmii-grp {/* RGMII */
fsl,pins = <
MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK0x1f
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC   0x3
@@ -744,6 +744,22 @@
>;
};
 
+   pinctrl_fec_rmii: dhcom-fec-rmii-grp {  /* RMII */
+   fsl,pins = <
+   MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC   0x3
+   MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO  0x3
+   MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
+   MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
+   MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL  0x91
+   MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x91
+   MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
+   MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
+   MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL  0x1f
+   /* Clock */
+   MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK
0x401f
+   >;
+   };
+
pinctrl_flexcan1: dhcom-flexcan1-grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX  0x154
-- 
2.39.1