Re: [PATCH v2 3/8] usb: xhci: octeon: Add DWC3 glue layer for Octeon
Hi Bin,
On 20.08.20 15:24, Bin Meng wrote:
Hi Stefan,
On Thu, Aug 20, 2020 at 7:45 PM Stefan Roese wrote:
Hi Bin,
On 20.08.20 11:07, Bin Meng wrote:
Hi Stefan,
On Thu, Aug 20, 2020 at 1:35 PM Stefan Roese wrote:
This patch adds the glue layer for the MIPS Octeon SoCs. Its ported
nits: It's
Ok.
mainly from the Linux code.
Signed-off-by: Stefan Roese
Cc: Bin Meng
Cc: Marek Vasut
---
(no changes since v1)
drivers/usb/host/Kconfig| 9 +
drivers/usb/host/Makefile | 1 +
drivers/usb/host/dwc3-octeon-glue.c | 396
3 files changed, 406 insertions(+)
create mode 100644 drivers/usb/host/dwc3-octeon-glue.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 1c374a7bd8..d71c12d888 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -46,6 +46,15 @@ config USB_XHCI_MVEBU
SoCs, which includes Armada8K, Armada3700 and other Armada
family SoCs.
+config USB_XHCI_OCTEON
+ bool "Support for Marvell Octeon family on-chip xHCI USB controller"
+ depends on ARCH_OCTEON
+ default y
+ help
+ Enables support for the on-chip xHCI controller on Marvell Octeon
+ family SoCs. This is a driver for the dwc3 to provide the glue logic
+ to configure the controller.
+
config USB_XHCI_PCI
bool "Support for PCI-based xHCI USB controller"
depends on DM_USB
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 29d4f87e38..a12e8f2702 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o
+obj-$(CONFIG_USB_XHCI_OCTEON) += dwc3-octeon-glue.o
# designware
obj-$(CONFIG_USB_DWC2) += dwc2.o
diff --git a/drivers/usb/host/dwc3-octeon-glue.c
b/drivers/usb/host/dwc3-octeon-glue.c
new file mode 100644
index 00..7b1ca7ee33
--- /dev/null
+++ b/drivers/usb/host/dwc3-octeon-glue.c
@@ -0,0 +1,396 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Octeon family DWC3 specific glue layer
+ *
+ * Copyright (C) 2020 Stefan Roese
+ *
+ * The lowlevel init code is based on the Linux driver octeon-usb.c by
nits: low-level
Ok.
+ * David Daney , which is:
+ * Copyright (C) 2010-2017 Cavium Networks
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CVMX_GPIO_BIT_CFGX(i) (0x000107000900ull + ((i) * 8))
+#define CVMX_GPIO_XBIT_CFGX(i) (0x000107000900ull + \
+((i) & 31) * 8 - 8 * 16)
+
+#define GPIO_BIT_CFG_TX_OE BIT_ULL(0)
+#define GPIO_BIT_CFG_OUTPUT_SELGENMASK_ULL(20, 16)
+
+#define UCTL_CTL_UCTL_RST BIT_ULL(0)
+#define UCTL_CTL_UAHC_RST BIT_ULL(1)
+#define UCTL_CTL_UPHY_RST BIT_ULL(2)
+#define UCTL_CTL_DRD_MODE BIT_ULL(3)
+#define UCTL_CTL_SCLK_EN BIT_ULL(4)
+#define UCTL_CTL_HS_POWER_EN BIT_ULL(12)
+#define UCTL_CTL_SS_POWER_EN BIT_ULL(14)
+#define UCTL_CTL_H_CLKDIV_SEL GENMASK_ULL(26, 24)
+#define UCTL_CTL_H_CLKDIV_RST BIT_ULL(28)
+#define UCTL_CTL_H_CLK_EN BIT_ULL(30)
+#define UCTL_CTL_REF_CLK_FSEL GENMASK_ULL(37, 32)
+#define UCTL_CTL_REF_CLK_DIV2 BIT_ULL(38)
+#define UCTL_CTL_REF_SSP_ENBIT_ULL(39)
+#define UCTL_CTL_MPLL_MULTIPLIER GENMASK_ULL(46, 40)
+#define UCTL_CTL_SSC_ENBIT_ULL(59)
+#define UCTL_CTL_REF_CLK_SEL GENMASK_ULL(61, 60)
+
+#define UCTL_HOST_CFG 0xe0
+#define UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN BIT_ULL(24)
+#define UCTL_HOST_CFG_PPC_EN BIT_ULL(25)
+
+#define UCTL_SHIM_CFG 0xe8
+#define UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK_ULL(1, 0)
+#define UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK_ULL(9, 8)
+
+#define OCTEON_H_CLKDIV_SEL8
+#define OCTEON_MIN_H_CLK_RATE 15000
+#define OCTEON_MAX_H_CLK_RATE 3
+
+static u8 clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
+
+static int dwc3_octeon_config_power(struct udevice *dev, void __iomem *base)
+{
+ u64 uctl_host_cfg;
+ u64 gpio_bit;
+ u32 gpio_pwr[3];
+ int gpio, len, power_active_low;
+ const struct device_node *node = dev_np(dev);
+ int index = ((u64)base >> 24) & 1;
+ void __iomem *gpio_bit_cfg;
+
+ if (of_find_property(node, "power", )) {
+ if (len == 12) {
+ dev_read_u32_array(dev, "power", gpio_pwr, 3);
+ power_active_low = gpio_pwr[2] & 0x01;
+ gpio = gpio_pwr[1];
+ } else if (len == 8) {
+
Re: [PATCH v2 3/8] usb: xhci: octeon: Add DWC3 glue layer for Octeon
Hi Stefan,
On Thu, Aug 20, 2020 at 7:45 PM Stefan Roese wrote:
>
> Hi Bin,
>
> On 20.08.20 11:07, Bin Meng wrote:
> > Hi Stefan,
> >
> > On Thu, Aug 20, 2020 at 1:35 PM Stefan Roese wrote:
> >>
> >> This patch adds the glue layer for the MIPS Octeon SoCs. Its ported
> >
> > nits: It's
>
> Ok.
>
> >> mainly from the Linux code.
> >>
> >> Signed-off-by: Stefan Roese
> >> Cc: Bin Meng
> >> Cc: Marek Vasut
> >> ---
> >>
> >> (no changes since v1)
> >>
> >> drivers/usb/host/Kconfig| 9 +
> >> drivers/usb/host/Makefile | 1 +
> >> drivers/usb/host/dwc3-octeon-glue.c | 396
> >> 3 files changed, 406 insertions(+)
> >> create mode 100644 drivers/usb/host/dwc3-octeon-glue.c
> >>
> >> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> >> index 1c374a7bd8..d71c12d888 100644
> >> --- a/drivers/usb/host/Kconfig
> >> +++ b/drivers/usb/host/Kconfig
> >> @@ -46,6 +46,15 @@ config USB_XHCI_MVEBU
> >>SoCs, which includes Armada8K, Armada3700 and other Armada
> >>family SoCs.
> >>
> >> +config USB_XHCI_OCTEON
> >> + bool "Support for Marvell Octeon family on-chip xHCI USB
> >> controller"
> >> + depends on ARCH_OCTEON
> >> + default y
> >> + help
> >> + Enables support for the on-chip xHCI controller on Marvell Octeon
> >> + family SoCs. This is a driver for the dwc3 to provide the glue
> >> logic
> >> + to configure the controller.
> >> +
> >> config USB_XHCI_PCI
> >> bool "Support for PCI-based xHCI USB controller"
> >> depends on DM_USB
> >> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> >> index 29d4f87e38..a12e8f2702 100644
> >> --- a/drivers/usb/host/Makefile
> >> +++ b/drivers/usb/host/Makefile
> >> @@ -56,6 +56,7 @@ obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
> >> obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
> >> obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
> >> obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o
> >> +obj-$(CONFIG_USB_XHCI_OCTEON) += dwc3-octeon-glue.o
> >>
> >> # designware
> >> obj-$(CONFIG_USB_DWC2) += dwc2.o
> >> diff --git a/drivers/usb/host/dwc3-octeon-glue.c
> >> b/drivers/usb/host/dwc3-octeon-glue.c
> >> new file mode 100644
> >> index 00..7b1ca7ee33
> >> --- /dev/null
> >> +++ b/drivers/usb/host/dwc3-octeon-glue.c
> >> @@ -0,0 +1,396 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * Octeon family DWC3 specific glue layer
> >> + *
> >> + * Copyright (C) 2020 Stefan Roese
> >> + *
> >> + * The lowlevel init code is based on the Linux driver octeon-usb.c by
> >
> > nits: low-level
>
> Ok.
>
> >> + * David Daney , which is:
> >> + * Copyright (C) 2010-2017 Cavium Networks
> >> + */
> >> +
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +
> >> +DECLARE_GLOBAL_DATA_PTR;
> >> +
> >> +#define CVMX_GPIO_BIT_CFGX(i) (0x000107000900ull + ((i) * 8))
> >> +#define CVMX_GPIO_XBIT_CFGX(i) (0x000107000900ull + \
> >> +((i) & 31) * 8 - 8 * 16)
> >> +
> >> +#define GPIO_BIT_CFG_TX_OE BIT_ULL(0)
> >> +#define GPIO_BIT_CFG_OUTPUT_SELGENMASK_ULL(20, 16)
> >> +
> >> +#define UCTL_CTL_UCTL_RST BIT_ULL(0)
> >> +#define UCTL_CTL_UAHC_RST BIT_ULL(1)
> >> +#define UCTL_CTL_UPHY_RST BIT_ULL(2)
> >> +#define UCTL_CTL_DRD_MODE BIT_ULL(3)
> >> +#define UCTL_CTL_SCLK_EN BIT_ULL(4)
> >> +#define UCTL_CTL_HS_POWER_EN BIT_ULL(12)
> >> +#define UCTL_CTL_SS_POWER_EN BIT_ULL(14)
> >> +#define UCTL_CTL_H_CLKDIV_SEL GENMASK_ULL(26, 24)
> >> +#define UCTL_CTL_H_CLKDIV_RST BIT_ULL(28)
> >> +#define UCTL_CTL_H_CLK_EN BIT_ULL(30)
> >> +#define UCTL_CTL_REF_CLK_FSEL GENMASK_ULL(37, 32)
> >> +#define UCTL_CTL_REF_CLK_DIV2 BIT_ULL(38)
> >> +#define UCTL_CTL_REF_SSP_ENBIT_ULL(39)
> >> +#define UCTL_CTL_MPLL_MULTIPLIER GENMASK_ULL(46, 40)
> >> +#define UCTL_CTL_SSC_ENBIT_ULL(59)
> >> +#define UCTL_CTL_REF_CLK_SEL GENMASK_ULL(61, 60)
> >> +
> >> +#define UCTL_HOST_CFG 0xe0
> >> +#define UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN BIT_ULL(24)
> >> +#define UCTL_HOST_CFG_PPC_EN BIT_ULL(25)
> >> +
> >> +#define UCTL_SHIM_CFG 0xe8
> >> +#define UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK_ULL(1, 0)
> >> +#define UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK_ULL(9, 8)
> >> +
> >> +#define OCTEON_H_CLKDIV_SEL8
> >> +#define OCTEON_MIN_H_CLK_RATE 15000
> >> +#define OCTEON_MAX_H_CLK_RATE 3
> >> +
> >> +static u8 clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
> >> +
> >> +static int dwc3_octeon_config_power(struct udevice *dev, void __iomem
>
Re: [PATCH v2 3/8] usb: xhci: octeon: Add DWC3 glue layer for Octeon
Hi Bin,
On 20.08.20 11:07, Bin Meng wrote:
Hi Stefan,
On Thu, Aug 20, 2020 at 1:35 PM Stefan Roese wrote:
This patch adds the glue layer for the MIPS Octeon SoCs. Its ported
nits: It's
Ok.
mainly from the Linux code.
Signed-off-by: Stefan Roese
Cc: Bin Meng
Cc: Marek Vasut
---
(no changes since v1)
drivers/usb/host/Kconfig| 9 +
drivers/usb/host/Makefile | 1 +
drivers/usb/host/dwc3-octeon-glue.c | 396
3 files changed, 406 insertions(+)
create mode 100644 drivers/usb/host/dwc3-octeon-glue.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 1c374a7bd8..d71c12d888 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -46,6 +46,15 @@ config USB_XHCI_MVEBU
SoCs, which includes Armada8K, Armada3700 and other Armada
family SoCs.
+config USB_XHCI_OCTEON
+ bool "Support for Marvell Octeon family on-chip xHCI USB controller"
+ depends on ARCH_OCTEON
+ default y
+ help
+ Enables support for the on-chip xHCI controller on Marvell Octeon
+ family SoCs. This is a driver for the dwc3 to provide the glue logic
+ to configure the controller.
+
config USB_XHCI_PCI
bool "Support for PCI-based xHCI USB controller"
depends on DM_USB
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 29d4f87e38..a12e8f2702 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o
+obj-$(CONFIG_USB_XHCI_OCTEON) += dwc3-octeon-glue.o
# designware
obj-$(CONFIG_USB_DWC2) += dwc2.o
diff --git a/drivers/usb/host/dwc3-octeon-glue.c
b/drivers/usb/host/dwc3-octeon-glue.c
new file mode 100644
index 00..7b1ca7ee33
--- /dev/null
+++ b/drivers/usb/host/dwc3-octeon-glue.c
@@ -0,0 +1,396 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Octeon family DWC3 specific glue layer
+ *
+ * Copyright (C) 2020 Stefan Roese
+ *
+ * The lowlevel init code is based on the Linux driver octeon-usb.c by
nits: low-level
Ok.
+ * David Daney , which is:
+ * Copyright (C) 2010-2017 Cavium Networks
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CVMX_GPIO_BIT_CFGX(i) (0x000107000900ull + ((i) * 8))
+#define CVMX_GPIO_XBIT_CFGX(i) (0x000107000900ull + \
+((i) & 31) * 8 - 8 * 16)
+
+#define GPIO_BIT_CFG_TX_OE BIT_ULL(0)
+#define GPIO_BIT_CFG_OUTPUT_SELGENMASK_ULL(20, 16)
+
+#define UCTL_CTL_UCTL_RST BIT_ULL(0)
+#define UCTL_CTL_UAHC_RST BIT_ULL(1)
+#define UCTL_CTL_UPHY_RST BIT_ULL(2)
+#define UCTL_CTL_DRD_MODE BIT_ULL(3)
+#define UCTL_CTL_SCLK_EN BIT_ULL(4)
+#define UCTL_CTL_HS_POWER_EN BIT_ULL(12)
+#define UCTL_CTL_SS_POWER_EN BIT_ULL(14)
+#define UCTL_CTL_H_CLKDIV_SEL GENMASK_ULL(26, 24)
+#define UCTL_CTL_H_CLKDIV_RST BIT_ULL(28)
+#define UCTL_CTL_H_CLK_EN BIT_ULL(30)
+#define UCTL_CTL_REF_CLK_FSEL GENMASK_ULL(37, 32)
+#define UCTL_CTL_REF_CLK_DIV2 BIT_ULL(38)
+#define UCTL_CTL_REF_SSP_ENBIT_ULL(39)
+#define UCTL_CTL_MPLL_MULTIPLIER GENMASK_ULL(46, 40)
+#define UCTL_CTL_SSC_ENBIT_ULL(59)
+#define UCTL_CTL_REF_CLK_SEL GENMASK_ULL(61, 60)
+
+#define UCTL_HOST_CFG 0xe0
+#define UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN BIT_ULL(24)
+#define UCTL_HOST_CFG_PPC_EN BIT_ULL(25)
+
+#define UCTL_SHIM_CFG 0xe8
+#define UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK_ULL(1, 0)
+#define UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK_ULL(9, 8)
+
+#define OCTEON_H_CLKDIV_SEL8
+#define OCTEON_MIN_H_CLK_RATE 15000
+#define OCTEON_MAX_H_CLK_RATE 3
+
+static u8 clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
+
+static int dwc3_octeon_config_power(struct udevice *dev, void __iomem *base)
+{
+ u64 uctl_host_cfg;
+ u64 gpio_bit;
+ u32 gpio_pwr[3];
+ int gpio, len, power_active_low;
+ const struct device_node *node = dev_np(dev);
+ int index = ((u64)base >> 24) & 1;
+ void __iomem *gpio_bit_cfg;
+
+ if (of_find_property(node, "power", )) {
+ if (len == 12) {
+ dev_read_u32_array(dev, "power", gpio_pwr, 3);
+ power_active_low = gpio_pwr[2] & 0x01;
+ gpio = gpio_pwr[1];
+ } else if (len == 8) {
+ dev_read_u32_array(dev, "power", gpio_pwr, 2);
+ power_active_low = 0;
+ gpio =
Re: [PATCH v2 3/8] usb: xhci: octeon: Add DWC3 glue layer for Octeon
Hi Stefan,
On Thu, Aug 20, 2020 at 1:35 PM Stefan Roese wrote:
>
> This patch adds the glue layer for the MIPS Octeon SoCs. Its ported
nits: It's
> mainly from the Linux code.
>
> Signed-off-by: Stefan Roese
> Cc: Bin Meng
> Cc: Marek Vasut
> ---
>
> (no changes since v1)
>
> drivers/usb/host/Kconfig| 9 +
> drivers/usb/host/Makefile | 1 +
> drivers/usb/host/dwc3-octeon-glue.c | 396
> 3 files changed, 406 insertions(+)
> create mode 100644 drivers/usb/host/dwc3-octeon-glue.c
>
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index 1c374a7bd8..d71c12d888 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -46,6 +46,15 @@ config USB_XHCI_MVEBU
> SoCs, which includes Armada8K, Armada3700 and other Armada
> family SoCs.
>
> +config USB_XHCI_OCTEON
> + bool "Support for Marvell Octeon family on-chip xHCI USB controller"
> + depends on ARCH_OCTEON
> + default y
> + help
> + Enables support for the on-chip xHCI controller on Marvell Octeon
> + family SoCs. This is a driver for the dwc3 to provide the glue logic
> + to configure the controller.
> +
> config USB_XHCI_PCI
> bool "Support for PCI-based xHCI USB controller"
> depends on DM_USB
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index 29d4f87e38..a12e8f2702 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -56,6 +56,7 @@ obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
> obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
> obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
> obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o
> +obj-$(CONFIG_USB_XHCI_OCTEON) += dwc3-octeon-glue.o
>
> # designware
> obj-$(CONFIG_USB_DWC2) += dwc2.o
> diff --git a/drivers/usb/host/dwc3-octeon-glue.c
> b/drivers/usb/host/dwc3-octeon-glue.c
> new file mode 100644
> index 00..7b1ca7ee33
> --- /dev/null
> +++ b/drivers/usb/host/dwc3-octeon-glue.c
> @@ -0,0 +1,396 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Octeon family DWC3 specific glue layer
> + *
> + * Copyright (C) 2020 Stefan Roese
> + *
> + * The lowlevel init code is based on the Linux driver octeon-usb.c by
nits: low-level
> + * David Daney , which is:
> + * Copyright (C) 2010-2017 Cavium Networks
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define CVMX_GPIO_BIT_CFGX(i) (0x000107000900ull + ((i) * 8))
> +#define CVMX_GPIO_XBIT_CFGX(i) (0x000107000900ull + \
> +((i) & 31) * 8 - 8 * 16)
> +
> +#define GPIO_BIT_CFG_TX_OE BIT_ULL(0)
> +#define GPIO_BIT_CFG_OUTPUT_SELGENMASK_ULL(20, 16)
> +
> +#define UCTL_CTL_UCTL_RST BIT_ULL(0)
> +#define UCTL_CTL_UAHC_RST BIT_ULL(1)
> +#define UCTL_CTL_UPHY_RST BIT_ULL(2)
> +#define UCTL_CTL_DRD_MODE BIT_ULL(3)
> +#define UCTL_CTL_SCLK_EN BIT_ULL(4)
> +#define UCTL_CTL_HS_POWER_EN BIT_ULL(12)
> +#define UCTL_CTL_SS_POWER_EN BIT_ULL(14)
> +#define UCTL_CTL_H_CLKDIV_SEL GENMASK_ULL(26, 24)
> +#define UCTL_CTL_H_CLKDIV_RST BIT_ULL(28)
> +#define UCTL_CTL_H_CLK_EN BIT_ULL(30)
> +#define UCTL_CTL_REF_CLK_FSEL GENMASK_ULL(37, 32)
> +#define UCTL_CTL_REF_CLK_DIV2 BIT_ULL(38)
> +#define UCTL_CTL_REF_SSP_ENBIT_ULL(39)
> +#define UCTL_CTL_MPLL_MULTIPLIER GENMASK_ULL(46, 40)
> +#define UCTL_CTL_SSC_ENBIT_ULL(59)
> +#define UCTL_CTL_REF_CLK_SEL GENMASK_ULL(61, 60)
> +
> +#define UCTL_HOST_CFG 0xe0
> +#define UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN BIT_ULL(24)
> +#define UCTL_HOST_CFG_PPC_EN BIT_ULL(25)
> +
> +#define UCTL_SHIM_CFG 0xe8
> +#define UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK_ULL(1, 0)
> +#define UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK_ULL(9, 8)
> +
> +#define OCTEON_H_CLKDIV_SEL8
> +#define OCTEON_MIN_H_CLK_RATE 15000
> +#define OCTEON_MAX_H_CLK_RATE 3
> +
> +static u8 clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
> +
> +static int dwc3_octeon_config_power(struct udevice *dev, void __iomem *base)
> +{
> + u64 uctl_host_cfg;
> + u64 gpio_bit;
> + u32 gpio_pwr[3];
> + int gpio, len, power_active_low;
> + const struct device_node *node = dev_np(dev);
> + int index = ((u64)base >> 24) & 1;
> + void __iomem *gpio_bit_cfg;
> +
> + if (of_find_property(node, "power", )) {
> + if (len == 12) {
> + dev_read_u32_array(dev, "power", gpio_pwr, 3);
> + power_active_low = gpio_pwr[2] & 0x01;
> + gpio = gpio_pwr[1];
> +
[PATCH v2 3/8] usb: xhci: octeon: Add DWC3 glue layer for Octeon
This patch adds the glue layer for the MIPS Octeon SoCs. Its ported
mainly from the Linux code.
Signed-off-by: Stefan Roese
Cc: Bin Meng
Cc: Marek Vasut
---
(no changes since v1)
drivers/usb/host/Kconfig| 9 +
drivers/usb/host/Makefile | 1 +
drivers/usb/host/dwc3-octeon-glue.c | 396
3 files changed, 406 insertions(+)
create mode 100644 drivers/usb/host/dwc3-octeon-glue.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 1c374a7bd8..d71c12d888 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -46,6 +46,15 @@ config USB_XHCI_MVEBU
SoCs, which includes Armada8K, Armada3700 and other Armada
family SoCs.
+config USB_XHCI_OCTEON
+ bool "Support for Marvell Octeon family on-chip xHCI USB controller"
+ depends on ARCH_OCTEON
+ default y
+ help
+ Enables support for the on-chip xHCI controller on Marvell Octeon
+ family SoCs. This is a driver for the dwc3 to provide the glue logic
+ to configure the controller.
+
config USB_XHCI_PCI
bool "Support for PCI-based xHCI USB controller"
depends on DM_USB
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 29d4f87e38..a12e8f2702 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o
+obj-$(CONFIG_USB_XHCI_OCTEON) += dwc3-octeon-glue.o
# designware
obj-$(CONFIG_USB_DWC2) += dwc2.o
diff --git a/drivers/usb/host/dwc3-octeon-glue.c
b/drivers/usb/host/dwc3-octeon-glue.c
new file mode 100644
index 00..7b1ca7ee33
--- /dev/null
+++ b/drivers/usb/host/dwc3-octeon-glue.c
@@ -0,0 +1,396 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Octeon family DWC3 specific glue layer
+ *
+ * Copyright (C) 2020 Stefan Roese
+ *
+ * The lowlevel init code is based on the Linux driver octeon-usb.c by
+ * David Daney , which is:
+ * Copyright (C) 2010-2017 Cavium Networks
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CVMX_GPIO_BIT_CFGX(i) (0x000107000900ull + ((i) * 8))
+#define CVMX_GPIO_XBIT_CFGX(i) (0x000107000900ull + \
+((i) & 31) * 8 - 8 * 16)
+
+#define GPIO_BIT_CFG_TX_OE BIT_ULL(0)
+#define GPIO_BIT_CFG_OUTPUT_SELGENMASK_ULL(20, 16)
+
+#define UCTL_CTL_UCTL_RST BIT_ULL(0)
+#define UCTL_CTL_UAHC_RST BIT_ULL(1)
+#define UCTL_CTL_UPHY_RST BIT_ULL(2)
+#define UCTL_CTL_DRD_MODE BIT_ULL(3)
+#define UCTL_CTL_SCLK_EN BIT_ULL(4)
+#define UCTL_CTL_HS_POWER_EN BIT_ULL(12)
+#define UCTL_CTL_SS_POWER_EN BIT_ULL(14)
+#define UCTL_CTL_H_CLKDIV_SEL GENMASK_ULL(26, 24)
+#define UCTL_CTL_H_CLKDIV_RST BIT_ULL(28)
+#define UCTL_CTL_H_CLK_EN BIT_ULL(30)
+#define UCTL_CTL_REF_CLK_FSEL GENMASK_ULL(37, 32)
+#define UCTL_CTL_REF_CLK_DIV2 BIT_ULL(38)
+#define UCTL_CTL_REF_SSP_ENBIT_ULL(39)
+#define UCTL_CTL_MPLL_MULTIPLIER GENMASK_ULL(46, 40)
+#define UCTL_CTL_SSC_ENBIT_ULL(59)
+#define UCTL_CTL_REF_CLK_SEL GENMASK_ULL(61, 60)
+
+#define UCTL_HOST_CFG 0xe0
+#define UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN BIT_ULL(24)
+#define UCTL_HOST_CFG_PPC_EN BIT_ULL(25)
+
+#define UCTL_SHIM_CFG 0xe8
+#define UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK_ULL(1, 0)
+#define UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK_ULL(9, 8)
+
+#define OCTEON_H_CLKDIV_SEL8
+#define OCTEON_MIN_H_CLK_RATE 15000
+#define OCTEON_MAX_H_CLK_RATE 3
+
+static u8 clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
+
+static int dwc3_octeon_config_power(struct udevice *dev, void __iomem *base)
+{
+ u64 uctl_host_cfg;
+ u64 gpio_bit;
+ u32 gpio_pwr[3];
+ int gpio, len, power_active_low;
+ const struct device_node *node = dev_np(dev);
+ int index = ((u64)base >> 24) & 1;
+ void __iomem *gpio_bit_cfg;
+
+ if (of_find_property(node, "power", )) {
+ if (len == 12) {
+ dev_read_u32_array(dev, "power", gpio_pwr, 3);
+ power_active_low = gpio_pwr[2] & 0x01;
+ gpio = gpio_pwr[1];
+ } else if (len == 8) {
+ dev_read_u32_array(dev, "power", gpio_pwr, 2);
+ power_active_low = 0;
+ gpio = gpio_pwr[1];
+ } else {
+ printf("dwc3 controller clock init failure\n");
+ return -EINVAL;
+ }
+
+
