Re: [PATCH v3] mtd: nand: Add NAND controller driver for OcteonTX
On 26.08.20 14:37, Stefan Roese wrote: From: Suneel Garapati Adds support for NAND controllers found on OcteonTX or OcteonTX2 SoC platforms. Also includes driver to support Hardware ECC using BCH HW engine found on these platforms. Signed-off-by: Aaron Williams Signed-off-by: Suneel Garapati Signed-off-by: Stefan Roese --- Series-changes: 3 - Add SoB from Stefan - Remove spdx.org line from comment - Remove inclusion of common.h header - Order header file inclusion - Misc minor checkpatch fixes - Fix warning in octeontx_cmd_queue_initialize() and now correctly initialize the cmd queue (Aaron) Series-changes: 1 - Change patch subject Applied to u-boot-marvell/master Thanks, Stefan drivers/mtd/nand/raw/Kconfig | 16 + drivers/mtd/nand/raw/Makefile|2 + drivers/mtd/nand/raw/octeontx_bch.c | 425 drivers/mtd/nand/raw/octeontx_bch.h | 131 ++ drivers/mtd/nand/raw/octeontx_bch_regs.h | 167 ++ drivers/mtd/nand/raw/octeontx_nand.c | 2257 ++ 6 files changed, 2998 insertions(+) create mode 100644 drivers/mtd/nand/raw/octeontx_bch.c create mode 100644 drivers/mtd/nand/raw/octeontx_bch.h create mode 100644 drivers/mtd/nand/raw/octeontx_bch_regs.h create mode 100644 drivers/mtd/nand/raw/octeontx_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 06b2ff972c..5d86fe470d 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -291,6 +291,22 @@ config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS This flag prevent U-boot reconfigure NAND flash controller and reuse the NAND timing from 1st stage bootloader. +config NAND_OCTEONTX + bool "Support for OcteonTX NAND controller" + select SYS_NAND_SELF_INIT + imply CMD_NAND + help +This enables Nand flash controller hardware found on the OcteonTX +processors. + +config NAND_OCTEONTX_HW_ECC + bool "Support Hardware ECC for OcteonTX NAND controller" + depends on NAND_OCTEONTX + default y + help +This enables Hardware BCH engine found on the OcteonTX processors to +support ECC for NAND flash controller. + config NAND_STM32_FMC2 bool "Support for NAND controller on STM32MP SoCs" depends on ARCH_STM32MP diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 9337f6482e..24c51b6924 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -58,6 +58,8 @@ obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o obj-$(CONFIG_NAND_MXC) += mxc_nand.o obj-$(CONFIG_NAND_MXS) += mxs_nand.o obj-$(CONFIG_NAND_MXS_DT) += mxs_nand_dt.o +obj-$(CONFIG_NAND_OCTEONTX) += octeontx_nand.o +obj-$(CONFIG_NAND_OCTEONTX_HW_ECC) += octeontx_bch.o obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o obj-$(CONFIG_NAND_SPEAR) += spr_nand.o obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o diff --git a/drivers/mtd/nand/raw/octeontx_bch.c b/drivers/mtd/nand/raw/octeontx_bch.c new file mode 100644 index 00..693706257c --- /dev/null +++ b/drivers/mtd/nand/raw/octeontx_bch.c @@ -0,0 +1,425 @@ +// SPDX-License-Identifier:GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "octeontx_bch.h" + +#ifdef DEBUG +# undef CONFIG_LOGLEVEL +# define CONFIG_LOGLEVEL 8 +#endif + +LIST_HEAD(octeontx_bch_devices); +static unsigned int num_vfs = BCH_NR_VF; +static void *bch_pf; +static void *bch_vf; +static void *token; +static bool bch_pf_initialized; +static bool bch_vf_initialized; + +static int pci_enable_sriov(struct udevice *dev, int nr_virtfn) +{ + int ret; + + ret = pci_sriov_init(dev, nr_virtfn); + if (ret) + printf("%s(%s): pci_sriov_init returned %d\n", __func__, + dev->name, ret); + return ret; +} + +void *octeontx_bch_getv(void) +{ + if (!bch_vf) + return NULL; + if (bch_vf_initialized && bch_pf_initialized) + return bch_vf; + else + return NULL; +} + +void octeontx_bch_putv(void *token) +{ + bch_vf_initialized = !!token; + bch_vf = token; +} + +void *octeontx_bch_getp(void) +{ + return token; +} + +void octeontx_bch_putp(void *token) +{ + bch_pf = token; + bch_pf_initialized = !!token; +} + +static int do_bch_init(struct bch_device *bch) +{ + return 0; +} + +static void bch_reset(struct bch_device *bch) +{ + writeq(1, bch->reg_base + BCH_CTL); + mdelay(2); +} + +static void bch_disable(struct bch_device *bch) +{ + writeq(~0ull, bch->reg_base + BCH_ERR_INT_ENA_W1C); + writeq(~0ull, bch->reg_base + BCH_ERR_INT); + bch_reset(bch); +} + +static u32
[PATCH v3] mtd: nand: Add NAND controller driver for OcteonTX
From: Suneel Garapati Adds support for NAND controllers found on OcteonTX or OcteonTX2 SoC platforms. Also includes driver to support Hardware ECC using BCH HW engine found on these platforms. Signed-off-by: Aaron Williams Signed-off-by: Suneel Garapati Signed-off-by: Stefan Roese --- Series-changes: 3 - Add SoB from Stefan - Remove spdx.org line from comment - Remove inclusion of common.h header - Order header file inclusion - Misc minor checkpatch fixes - Fix warning in octeontx_cmd_queue_initialize() and now correctly initialize the cmd queue (Aaron) Series-changes: 1 - Change patch subject drivers/mtd/nand/raw/Kconfig | 16 + drivers/mtd/nand/raw/Makefile|2 + drivers/mtd/nand/raw/octeontx_bch.c | 425 drivers/mtd/nand/raw/octeontx_bch.h | 131 ++ drivers/mtd/nand/raw/octeontx_bch_regs.h | 167 ++ drivers/mtd/nand/raw/octeontx_nand.c | 2257 ++ 6 files changed, 2998 insertions(+) create mode 100644 drivers/mtd/nand/raw/octeontx_bch.c create mode 100644 drivers/mtd/nand/raw/octeontx_bch.h create mode 100644 drivers/mtd/nand/raw/octeontx_bch_regs.h create mode 100644 drivers/mtd/nand/raw/octeontx_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 06b2ff972c..5d86fe470d 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -291,6 +291,22 @@ config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS This flag prevent U-boot reconfigure NAND flash controller and reuse the NAND timing from 1st stage bootloader. +config NAND_OCTEONTX + bool "Support for OcteonTX NAND controller" + select SYS_NAND_SELF_INIT + imply CMD_NAND + help +This enables Nand flash controller hardware found on the OcteonTX +processors. + +config NAND_OCTEONTX_HW_ECC + bool "Support Hardware ECC for OcteonTX NAND controller" + depends on NAND_OCTEONTX + default y + help +This enables Hardware BCH engine found on the OcteonTX processors to +support ECC for NAND flash controller. + config NAND_STM32_FMC2 bool "Support for NAND controller on STM32MP SoCs" depends on ARCH_STM32MP diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 9337f6482e..24c51b6924 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -58,6 +58,8 @@ obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o obj-$(CONFIG_NAND_MXC) += mxc_nand.o obj-$(CONFIG_NAND_MXS) += mxs_nand.o obj-$(CONFIG_NAND_MXS_DT) += mxs_nand_dt.o +obj-$(CONFIG_NAND_OCTEONTX) += octeontx_nand.o +obj-$(CONFIG_NAND_OCTEONTX_HW_ECC) += octeontx_bch.o obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o obj-$(CONFIG_NAND_SPEAR) += spr_nand.o obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o diff --git a/drivers/mtd/nand/raw/octeontx_bch.c b/drivers/mtd/nand/raw/octeontx_bch.c new file mode 100644 index 00..693706257c --- /dev/null +++ b/drivers/mtd/nand/raw/octeontx_bch.c @@ -0,0 +1,425 @@ +// SPDX-License-Identifier:GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "octeontx_bch.h" + +#ifdef DEBUG +# undef CONFIG_LOGLEVEL +# define CONFIG_LOGLEVEL 8 +#endif + +LIST_HEAD(octeontx_bch_devices); +static unsigned int num_vfs = BCH_NR_VF; +static void *bch_pf; +static void *bch_vf; +static void *token; +static bool bch_pf_initialized; +static bool bch_vf_initialized; + +static int pci_enable_sriov(struct udevice *dev, int nr_virtfn) +{ + int ret; + + ret = pci_sriov_init(dev, nr_virtfn); + if (ret) + printf("%s(%s): pci_sriov_init returned %d\n", __func__, + dev->name, ret); + return ret; +} + +void *octeontx_bch_getv(void) +{ + if (!bch_vf) + return NULL; + if (bch_vf_initialized && bch_pf_initialized) + return bch_vf; + else + return NULL; +} + +void octeontx_bch_putv(void *token) +{ + bch_vf_initialized = !!token; + bch_vf = token; +} + +void *octeontx_bch_getp(void) +{ + return token; +} + +void octeontx_bch_putp(void *token) +{ + bch_pf = token; + bch_pf_initialized = !!token; +} + +static int do_bch_init(struct bch_device *bch) +{ + return 0; +} + +static void bch_reset(struct bch_device *bch) +{ + writeq(1, bch->reg_base + BCH_CTL); + mdelay(2); +} + +static void bch_disable(struct bch_device *bch) +{ + writeq(~0ull, bch->reg_base + BCH_ERR_INT_ENA_W1C); + writeq(~0ull, bch->reg_base + BCH_ERR_INT); + bch_reset(bch); +} + +static u32 bch_check_bist_status(struct bch_device *bch) +{ + return readq(bch->reg_base + BCH_BIST_RESULT); +} + +static int