Number of Qualcomm ARMv7 SoC-s did not use PSCI but rather used PSHOLD
(Qualcomm Power Supply Hold Reset) bit to trigger reset or poweroff.
Qualcomm IPQ40XX is one of them, so provide a simple sysreset driver based
on the upstream Linux one, it is DT compatible as well.
Signed-off-by: Robert Marko
Reviewed-by: Caleb Connolly
---
Changes in v3:
* Drop
Changes in v2:
* Use QCOM instead of MSM naming
drivers/sysreset/Kconfig| 6 +++
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_qcom-pshold.c | 55 +
3 files changed, 62 insertions(+)
create mode 100644 drivers/sysreset/sysreset_qcom-pshold.c
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index b64bfadb20..121194e441 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -240,6 +240,12 @@ config SYSRESET_RAA215300
help
Add support for the system reboot via the Renesas RAA215300 PMIC.
+config SYSRESET_QCOM_PSHOLD
+ bool "Support sysreset for Qualcomm SoCs via PSHOLD"
+ depends on ARCH_IPQ40XX
+ help
+ Add support for the system reboot on Qualcomm SoCs via PSHOLD.
+
endif
endmenu
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index d59299aa31..a6a0584585 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -29,4 +29,5 @@ obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_AT91) += sysreset_at91.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
obj-$(CONFIG_SYSRESET_RAA215300) += sysreset_raa215300.o
+obj-$(CONFIG_SYSRESET_QCOM_PSHOLD) += sysreset_qcom-pshold.o
obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
diff --git a/drivers/sysreset/sysreset_qcom-pshold.c
b/drivers/sysreset/sysreset_qcom-pshold.c
new file mode 100644
index 00..4529047853
--- /dev/null
+++ b/drivers/sysreset/sysreset_qcom-pshold.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm PSHOLD reset driver
+ *
+ * Copyright (c) 2024 Sartura Ltd.
+ *
+ * Author: Robert Marko
+ * Based on the Linux msm-poweroff driver.
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+struct qcom_pshold_priv {
+ phys_addr_t base;
+};
+
+static int qcom_pshold_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct qcom_pshold_priv *priv = dev_get_priv(dev);
+
+ writel(0, priv->base);
+ mdelay(1);
+
+ return 0;
+}
+
+static struct sysreset_ops qcom_pshold_ops = {
+ .request = qcom_pshold_request,
+};
+
+static int qcom_pshold_probe(struct udevice *dev)
+{
+ struct qcom_pshold_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr(dev);
+ return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
+}
+
+static const struct udevice_id qcom_pshold_ids[] = {
+ { .compatible = "qcom,pshold", },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(qcom_pshold) = {
+ .name = "qcom_pshold",
+ .id = UCLASS_SYSRESET,
+ .of_match = qcom_pshold_ids,
+ .probe = qcom_pshold_probe,
+ .priv_auto = sizeof(struct qcom_pshold_priv),
+ .ops= _pshold_ops,
+};
--
2.45.0
