Re: [PATCH v3 02/11] net: dwc_eth_qos: Add StarFive ethernet driver glue layer
On Fri, Apr 28, 2023 at 5:25 AM Yanhong Wang
wrote:
>
> The StarFive ETHQOS hardware has its own clock and reset,so add a
> corresponding glue driver to configure them.
>
> Signed-off-by: Yanhong Wang
> ---
> drivers/net/Kconfig| 7 +
> drivers/net/Makefile | 1 +
> drivers/net/dwc_eth_qos.c | 6 +
> drivers/net/dwc_eth_qos.h | 1 +
> drivers/net/dwc_eth_qos_starfive.c | 249 +
> 5 files changed, 264 insertions(+)
> create mode 100644 drivers/net/dwc_eth_qos_starfive.c
>
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index 09039a283e..5540f0ea18 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -249,6 +249,13 @@ config DWC_ETH_QOS_QCOM
> The Synopsys Designware Ethernet QOS IP block with specific
> configuration used in Qcom QCS404 SoC.
>
> +config DWC_ETH_QOS_STARFIVE
> + bool "Synopsys DWC Ethernet QOS device support for STARFIVE"
> + depends on DWC_ETH_QOS
> + help
> + The Synopsys Designware Ethernet QOS IP block with specific
> + configuration used in STARFIVE JH7110 soc.
> +
> config E1000
> bool "Intel PRO/1000 Gigabit Ethernet support"
> depends on PCI
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index 46a40e2ed9..d4af253b6f 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -21,6 +21,7 @@ obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
> obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
> obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
> obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
> +obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
> obj-$(CONFIG_E1000) += e1000.o
> obj-$(CONFIG_E1000_SPI) += e1000_spi.o
> obj-$(CONFIG_EEPRO100) += eepro100.o
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> index ec58697b31..8060a4e782 100644
> --- a/drivers/net/dwc_eth_qos.c
> +++ b/drivers/net/dwc_eth_qos.c
> @@ -1713,6 +1713,12 @@ static const struct udevice_id eqos_ids[] = {
> .data = (ulong)&eqos_qcom_config
> },
> #endif
> +#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STARFIVE)
> + {
> + .compatible = "starfive,jh7110-dwmac",
> + .data = (ulong)&eqos_jh7110_config
> + },
> +#endif
>
> { }
> };
> diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
> index fddbe9336c..a6b719af80 100644
> --- a/drivers/net/dwc_eth_qos.h
> +++ b/drivers/net/dwc_eth_qos.h
> @@ -289,3 +289,4 @@ int eqos_null_ops(struct udevice *dev);
>
> extern struct eqos_config eqos_imx_config;
> extern struct eqos_config eqos_qcom_config;
> +extern struct eqos_config eqos_jh7110_config;
> diff --git a/drivers/net/dwc_eth_qos_starfive.c
> b/drivers/net/dwc_eth_qos_starfive.c
> new file mode 100644
> index 00..5be8ac0f1a
> --- /dev/null
> +++ b/drivers/net/dwc_eth_qos_starfive.c
> @@ -0,0 +1,249 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> + * Author: Yanhong Wang
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "dwc_eth_qos.h"
> +
> +#define STARFIVE_DWMAC_PHY_INFT_RGMII 0x1
> +#define STARFIVE_DWMAC_PHY_INFT_RMII 0x4
> +#define STARFIVE_DWMAC_PHY_INFT_FIELD 0x7U
> +
> +struct starfive_platform_data {
> + struct regmap *regmap;
> + struct reset_ctl_bulk resets;
> + struct clk_bulk clks;
> + phy_interface_t interface;
> + u32 offset;
> + u32 shift;
> + bool tx_use_rgmii_clk;
> +};
> +
> +static int eqos_interface_init_jh7110(struct udevice *dev)
> +{
> + struct eth_pdata *pdata = dev_get_plat(dev);
> + struct starfive_platform_data *data = pdata->priv_pdata;
> + struct ofnode_phandle_args args;
> + unsigned int mode;
> + int ret;
> +
> + switch (data->interface) {
> + case PHY_INTERFACE_MODE_RMII:
> + mode = STARFIVE_DWMAC_PHY_INFT_RMII;
> + break;
> +
> + case PHY_INTERFACE_MODE_RGMII:
> + case PHY_INTERFACE_MODE_RGMII_ID:
> + mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
> + break;
> +
> + default:
> + return -EINVAL;
> + }
> +
> + ret = dev_read_phandle_with_args(dev, "starfive,syscon", NULL,
> +2, 0, &args);
> + if (ret)
> + return ret;
> +
> + if (args.args_count != 2)
> + return -EINVAL;
> +
> + data->offset = args.args[0];
> + data->shift = args.args[1];
> + data->regmap = syscon_regmap_lookup_by_phandle(dev,
> "starfive,syscon");
> + if (IS_ERR(data->regmap)) {
> + ret = PTR_ERR(data->regmap);
> + pr_err("Failed to get regmap: %d\n", ret);
> + return ret;
> + }
> +
> + return regmap_update_bit
[PATCH v3 02/11] net: dwc_eth_qos: Add StarFive ethernet driver glue layer
The StarFive ETHQOS hardware has its own clock and reset,so add a
corresponding glue driver to configure them.
Signed-off-by: Yanhong Wang
---
drivers/net/Kconfig| 7 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 6 +
drivers/net/dwc_eth_qos.h | 1 +
drivers/net/dwc_eth_qos_starfive.c | 249 +
5 files changed, 264 insertions(+)
create mode 100644 drivers/net/dwc_eth_qos_starfive.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 09039a283e..5540f0ea18 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -249,6 +249,13 @@ config DWC_ETH_QOS_QCOM
The Synopsys Designware Ethernet QOS IP block with specific
configuration used in Qcom QCS404 SoC.
+config DWC_ETH_QOS_STARFIVE
+ bool "Synopsys DWC Ethernet QOS device support for STARFIVE"
+ depends on DWC_ETH_QOS
+ help
+ The Synopsys Designware Ethernet QOS IP block with specific
+ configuration used in STARFIVE JH7110 soc.
+
config E1000
bool "Intel PRO/1000 Gigabit Ethernet support"
depends on PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 46a40e2ed9..d4af253b6f 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
+obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index ec58697b31..8060a4e782 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1713,6 +1713,12 @@ static const struct udevice_id eqos_ids[] = {
.data = (ulong)&eqos_qcom_config
},
#endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STARFIVE)
+ {
+ .compatible = "starfive,jh7110-dwmac",
+ .data = (ulong)&eqos_jh7110_config
+ },
+#endif
{ }
};
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index fddbe9336c..a6b719af80 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -289,3 +289,4 @@ int eqos_null_ops(struct udevice *dev);
extern struct eqos_config eqos_imx_config;
extern struct eqos_config eqos_qcom_config;
+extern struct eqos_config eqos_jh7110_config;
diff --git a/drivers/net/dwc_eth_qos_starfive.c
b/drivers/net/dwc_eth_qos_starfive.c
new file mode 100644
index 00..5be8ac0f1a
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_starfive.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dwc_eth_qos.h"
+
+#define STARFIVE_DWMAC_PHY_INFT_RGMII 0x1
+#define STARFIVE_DWMAC_PHY_INFT_RMII 0x4
+#define STARFIVE_DWMAC_PHY_INFT_FIELD 0x7U
+
+struct starfive_platform_data {
+ struct regmap *regmap;
+ struct reset_ctl_bulk resets;
+ struct clk_bulk clks;
+ phy_interface_t interface;
+ u32 offset;
+ u32 shift;
+ bool tx_use_rgmii_clk;
+};
+
+static int eqos_interface_init_jh7110(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct starfive_platform_data *data = pdata->priv_pdata;
+ struct ofnode_phandle_args args;
+ unsigned int mode;
+ int ret;
+
+ switch (data->interface) {
+ case PHY_INTERFACE_MODE_RMII:
+ mode = STARFIVE_DWMAC_PHY_INFT_RMII;
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ ret = dev_read_phandle_with_args(dev, "starfive,syscon", NULL,
+2, 0, &args);
+ if (ret)
+ return ret;
+
+ if (args.args_count != 2)
+ return -EINVAL;
+
+ data->offset = args.args[0];
+ data->shift = args.args[1];
+ data->regmap = syscon_regmap_lookup_by_phandle(dev, "starfive,syscon");
+ if (IS_ERR(data->regmap)) {
+ ret = PTR_ERR(data->regmap);
+ pr_err("Failed to get regmap: %d\n", ret);
+ return ret;
+ }
+
+ return regmap_update_bits(data->regmap, data->offset,
+ STARFIVE_DWMAC_PHY_INFT_FIELD << data->shift,
+ mode << data->shift);
+}
+
+static int eqos_set_tx_clk_speed_jh7110(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+
