Re: [PATCH v4 1/3] starfive: pci: Add StarFive JH7110 pcie driver
On 2023/4/12 5:29, Pali Rohár wrote:
> Hello!
>
> On Tuesday 11 April 2023 09:02:07 Minda Chen wrote:
>> +int starfive_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
>> + uint offset, ulong value,
>> + enum pci_size_t size)
>> +{
>> +struct starfive_pcie *priv = dev_get_priv(udev);
>> +int ret;
>> +
>> +ret = pci_generic_mmap_write_config(udev, starfive_pcie_conf_address,
>> +bdf, offset, value, size);
>> +
>> +if (!ret && offset == PCI_SECONDARY_BUS) {
>> +priv->sec_busno = value & 0xff;
>> +debug("Secondary bus number was changed to %d\n",
>> + priv->sec_busno);
>> +}
>
> This block of code contains two issues:
>
> 1) If secondary bus is changed by the 16-bit or 32-bit write operation
>then this condition does not catch it.
>
> 2) priv->sec_busno is used just for checking if driver is going to
>access device on secondary bus of the Root Port. But this code
>updates priv->sec_busno also for write to _any_ device on any bus,
>not just when updating Root Port device. So it breaks support for
>non-trivial PCIe hierarchy which contains e.g. PCIe switch (e.g. when
>changing configuration of the virtual PCI-to-PCI bridge device of
>PCIe switch, which is behind the secondary bus of the Root Port).
>
> So you need something like this:
>
> if (!ret &&
> PCI_BUS(bdf) == dev_seq(udev) && PCI_DEV(bdf) == 0 && PCI_FUNC(bdf)
> == 0 &&
> (offset == PCI_SECONDARY_BUS || (offset == PCI_PRIMARY_BUS && size !=
> PCI_SIZE_8)) {
> priv->sec_busno = ((offset == PCI_PRIMARY_BUS) ? (value >> 8) :
> value) & 0xff;
> debug("Secondary bus number was changed to %d\n", pcie->sec_busno);
> }
>
> You have to update priv->sec_busno only when write request is for the
> Root Port. And you need to catch also 16-bit or 32-bit write operation
> to the PCI_PRIMARY_BUS register. It is because PCI_SECONDARY_BUS reg
> is (PCI_PRIMARY_BUS+2) and (PCI_SECONDARY_BUS & ~3) == PCI_PRIMARY_BUS
>
I will change like this. Thank you very much.
>> +return ret;
>> +}
Re: [PATCH v4 1/3] starfive: pci: Add StarFive JH7110 pcie driver
On 2023/4/11 13:20, Bin Meng wrote:
> On Tue, Apr 11, 2023 at 11:53 AM Minda Chen
> wrote:
>>
>>
>>
>> On 2023/4/11 10:55, Bin Meng wrote:
>> > On Tue, Apr 11, 2023 at 9:03 AM Minda Chen
>> > wrote:
>> >>
>> >> From: Mason Huo
>> >>
>> >> Add pcie driver for StarFive JH7110, the driver depends on
>> >> starfive gpio, pinctrl, clk and reset driver to do init.
>> >>
>> >> Several devices are tested:
>> >> a) M.2 NVMe SSD
>> >> b) Realtek 8169 Ethernet adapter.
>> >>
>> >> Signed-off-by: Mason Huo
>> >> Signed-off-by: Minda Chen
>> >> ---
>> >> drivers/pci/Kconfig| 9 +
>> >> drivers/pci/Makefile | 1 +
>> >> drivers/pci/pcie_starfive_jh7110.c | 465 +
>> >> 3 files changed, 475 insertions(+)
>> >> create mode 100644 drivers/pci/pcie_starfive_jh7110.c
>> >>
>> >> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
>> >> index ef328d2652..f37b6baa25 100644
>> >> --- a/drivers/pci/Kconfig
>> >> +++ b/drivers/pci/Kconfig
>> >> @@ -374,4 +374,13 @@ config PCIE_UNIPHIER
>> >> Say Y here if you want to enable PCIe controller support on
>> >> UniPhier SoCs.
>> >>
>> >> +config PCIE_STARFIVE_JH7110
>> >> + bool "Enable Starfive JH7110 PCIe driver"
>> >> + imply STARFIVE_JH7110
>> >> + imply CLK_JH7110
>> >> + imply RESET_JH7110
>> >> + help
>> >> + Say Y here if you want to enable PCIe controller support on
>> >> + StarFive JH7110 SoC.
>> >> +
>> >> endif
>> >> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
>> >> index 49506e7ba5..bbe3323bb5 100644
>> >> --- a/drivers/pci/Makefile
>> >> +++ b/drivers/pci/Makefile
>> >> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
>> >> obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
>> >> obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
>> >> obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
>> >> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
>> >> diff --git a/drivers/pci/pcie_starfive_jh7110.c
>> >> b/drivers/pci/pcie_starfive_jh7110.c
>> >> new file mode 100644
>> >> index 00..130181013e
>> >> --- /dev/null
>> >> +++ b/drivers/pci/pcie_starfive_jh7110.c
>> >> @@ -0,0 +1,465 @@
>> >> +// SPDX-License-Identifier: GPL-2.0+
>> >> +/*
>> >> + * StarFive PLDA PCIe host controller driver
>> >> + *
>> >> + * Copyright (c) 2023 Starfive, Inc.
>> >> + * Author: Mason Huo
>> >> + *
>> >> + */
>> >> +
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +
>> >> +DECLARE_GLOBAL_DATA_PTR;
>> >> +
>> >> +#define GEN_SETTINGS 0x80
>> >> +#define PCIE_PCI_IDS 0x9C
>> >> +#define PCIE_WINROM0xFC
>> >> +#define PMSG_SUPPORT_RX0x3F0
>> >> +#define PCI_MISC 0xB4
>> >> +
>> >> +#define PLDA_EP_ENABLE 0
>> >> +#define PLDA_RP_ENABLE 1
>> >> +
>> >> +#define IDS_CLASS_CODE_SHIFT 8
>> >> +
>> >> +#define PREF_MEM_WIN_64_SUPPORTBIT(3)
>> >> +#define PMSG_LTR_SUPPORT BIT(2)
>> >> +#define PLDA_FUNCTION_DIS BIT(15)
>> >> +#define PLDA_FUNC_NUM 4
>> >> +#define PLDA_PHY_FUNC_SHIFT9
>> >> +
>> >> +#define XR3PCI_ATR_AXI4_SLV0 0x800
>> >> +#define XR3PCI_ATR_SRC_ADDR_LOW0x0
>> >> +#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
>> >> +#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
>> >> +#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
>> >> +#define XR3PCI_ATR_TRSL_PARAM 0x10
>> >> +#define XR3PCI_ATR_TABLE_OFFSET0x20
>> >> +#define XR3PCI_ATR_MAX_TABLE_NUM 8
>> >> +
>> >> +#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
>> >> +#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12)
>> >> +#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12)
>> >> +#define XR3_PCI_ECAM_SIZE 28
>> >> +#define XR3PCI_ATR_TRSL_DIRBIT(22)
>> >> +/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
>> >> +#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
>> >> +#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
>> >> +
>> >> +/* system control */
>> >> +#define STG_SYSCON_K_RP_NEP_MASK BIT(8)
>> >> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8)
>> >> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8
>> >> +#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0)
>> >> +#define STG_SYSCON_CLKREQ_MASK BIT(22)
>> >> +#define STG_SYSCON_CKREF_SRC_SHIFT 18
>> >> +#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18)
>> >> +
>> >> +struct starfive_pcie {
>> >> + struct udevice *dev;
>> >> +
>> >> + void __iomem *reg_base;
>> >> + void __iomem *cfg_base;
>>
Re: [PATCH v4 1/3] starfive: pci: Add StarFive JH7110 pcie driver
Hello!
On Tuesday 11 April 2023 09:02:07 Minda Chen wrote:
> +int starfive_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
> +uint offset, ulong value,
> +enum pci_size_t size)
> +{
> + struct starfive_pcie *priv = dev_get_priv(udev);
> + int ret;
> +
> + ret = pci_generic_mmap_write_config(udev, starfive_pcie_conf_address,
> + bdf, offset, value, size);
> +
> + if (!ret && offset == PCI_SECONDARY_BUS) {
> + priv->sec_busno = value & 0xff;
> + debug("Secondary bus number was changed to %d\n",
> + priv->sec_busno);
> + }
This block of code contains two issues:
1) If secondary bus is changed by the 16-bit or 32-bit write operation
then this condition does not catch it.
2) priv->sec_busno is used just for checking if driver is going to
access device on secondary bus of the Root Port. But this code
updates priv->sec_busno also for write to _any_ device on any bus,
not just when updating Root Port device. So it breaks support for
non-trivial PCIe hierarchy which contains e.g. PCIe switch (e.g. when
changing configuration of the virtual PCI-to-PCI bridge device of
PCIe switch, which is behind the secondary bus of the Root Port).
So you need something like this:
if (!ret &&
PCI_BUS(bdf) == dev_seq(udev) && PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) ==
0 &&
(offset == PCI_SECONDARY_BUS || (offset == PCI_PRIMARY_BUS && size !=
PCI_SIZE_8)) {
priv->sec_busno = ((offset == PCI_PRIMARY_BUS) ? (value >> 8) : value)
& 0xff;
debug("Secondary bus number was changed to %d\n", pcie->sec_busno);
}
You have to update priv->sec_busno only when write request is for the
Root Port. And you need to catch also 16-bit or 32-bit write operation
to the PCI_PRIMARY_BUS register. It is because PCI_SECONDARY_BUS reg
is (PCI_PRIMARY_BUS+2) and (PCI_SECONDARY_BUS & ~3) == PCI_PRIMARY_BUS
> + return ret;
> +}
Re: [PATCH v4 1/3] starfive: pci: Add StarFive JH7110 pcie driver
On Tue, Apr 11, 2023 at 11:53 AM Minda Chen wrote:
>
>
>
> On 2023/4/11 10:55, Bin Meng wrote:
> > On Tue, Apr 11, 2023 at 9:03 AM Minda Chen
> > wrote:
> >>
> >> From: Mason Huo
> >>
> >> Add pcie driver for StarFive JH7110, the driver depends on
> >> starfive gpio, pinctrl, clk and reset driver to do init.
> >>
> >> Several devices are tested:
> >> a) M.2 NVMe SSD
> >> b) Realtek 8169 Ethernet adapter.
> >>
> >> Signed-off-by: Mason Huo
> >> Signed-off-by: Minda Chen
> >> ---
> >> drivers/pci/Kconfig| 9 +
> >> drivers/pci/Makefile | 1 +
> >> drivers/pci/pcie_starfive_jh7110.c | 465 +
> >> 3 files changed, 475 insertions(+)
> >> create mode 100644 drivers/pci/pcie_starfive_jh7110.c
> >>
> >> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> >> index ef328d2652..f37b6baa25 100644
> >> --- a/drivers/pci/Kconfig
> >> +++ b/drivers/pci/Kconfig
> >> @@ -374,4 +374,13 @@ config PCIE_UNIPHIER
> >> Say Y here if you want to enable PCIe controller support on
> >> UniPhier SoCs.
> >>
> >> +config PCIE_STARFIVE_JH7110
> >> + bool "Enable Starfive JH7110 PCIe driver"
> >> + imply STARFIVE_JH7110
> >> + imply CLK_JH7110
> >> + imply RESET_JH7110
> >> + help
> >> + Say Y here if you want to enable PCIe controller support on
> >> + StarFive JH7110 SoC.
> >> +
> >> endif
> >> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> >> index 49506e7ba5..bbe3323bb5 100644
> >> --- a/drivers/pci/Makefile
> >> +++ b/drivers/pci/Makefile
> >> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
> >> obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
> >> obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
> >> obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
> >> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
> >> diff --git a/drivers/pci/pcie_starfive_jh7110.c
> >> b/drivers/pci/pcie_starfive_jh7110.c
> >> new file mode 100644
> >> index 00..130181013e
> >> --- /dev/null
> >> +++ b/drivers/pci/pcie_starfive_jh7110.c
> >> @@ -0,0 +1,465 @@
> >> +// SPDX-License-Identifier: GPL-2.0+
> >> +/*
> >> + * StarFive PLDA PCIe host controller driver
> >> + *
> >> + * Copyright (c) 2023 Starfive, Inc.
> >> + * Author: Mason Huo
> >> + *
> >> + */
> >> +
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +
> >> +DECLARE_GLOBAL_DATA_PTR;
> >> +
> >> +#define GEN_SETTINGS 0x80
> >> +#define PCIE_PCI_IDS 0x9C
> >> +#define PCIE_WINROM0xFC
> >> +#define PMSG_SUPPORT_RX0x3F0
> >> +#define PCI_MISC 0xB4
> >> +
> >> +#define PLDA_EP_ENABLE 0
> >> +#define PLDA_RP_ENABLE 1
> >> +
> >> +#define IDS_CLASS_CODE_SHIFT 8
> >> +
> >> +#define PREF_MEM_WIN_64_SUPPORTBIT(3)
> >> +#define PMSG_LTR_SUPPORT BIT(2)
> >> +#define PLDA_FUNCTION_DIS BIT(15)
> >> +#define PLDA_FUNC_NUM 4
> >> +#define PLDA_PHY_FUNC_SHIFT9
> >> +
> >> +#define XR3PCI_ATR_AXI4_SLV0 0x800
> >> +#define XR3PCI_ATR_SRC_ADDR_LOW0x0
> >> +#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
> >> +#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
> >> +#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
> >> +#define XR3PCI_ATR_TRSL_PARAM 0x10
> >> +#define XR3PCI_ATR_TABLE_OFFSET0x20
> >> +#define XR3PCI_ATR_MAX_TABLE_NUM 8
> >> +
> >> +#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
> >> +#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12)
> >> +#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12)
> >> +#define XR3_PCI_ECAM_SIZE 28
> >> +#define XR3PCI_ATR_TRSL_DIRBIT(22)
> >> +/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
> >> +#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
> >> +#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
> >> +
> >> +/* system control */
> >> +#define STG_SYSCON_K_RP_NEP_MASK BIT(8)
> >> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8)
> >> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8
> >> +#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0)
> >> +#define STG_SYSCON_CLKREQ_MASK BIT(22)
> >> +#define STG_SYSCON_CKREF_SRC_SHIFT 18
> >> +#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18)
> >> +
> >> +struct starfive_pcie {
> >> + struct udevice *dev;
> >> +
> >> + void __iomem *reg_base;
> >> + void __iomem *cfg_base;
> >> +
> >> + struct regmap *regmap;
> >> + u32 stg_arfun;
> >> + u32 stg_awfun;
> >> + u32 stg_rp_nep;
> >> +
> >> + struct clk_bulk clks;
> >> +
Re: [PATCH v4 1/3] starfive: pci: Add StarFive JH7110 pcie driver
On 2023/4/11 10:55, Bin Meng wrote:
> On Tue, Apr 11, 2023 at 9:03 AM Minda Chen
> wrote:
>>
>> From: Mason Huo
>>
>> Add pcie driver for StarFive JH7110, the driver depends on
>> starfive gpio, pinctrl, clk and reset driver to do init.
>>
>> Several devices are tested:
>> a) M.2 NVMe SSD
>> b) Realtek 8169 Ethernet adapter.
>>
>> Signed-off-by: Mason Huo
>> Signed-off-by: Minda Chen
>> ---
>> drivers/pci/Kconfig| 9 +
>> drivers/pci/Makefile | 1 +
>> drivers/pci/pcie_starfive_jh7110.c | 465 +
>> 3 files changed, 475 insertions(+)
>> create mode 100644 drivers/pci/pcie_starfive_jh7110.c
>>
>> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
>> index ef328d2652..f37b6baa25 100644
>> --- a/drivers/pci/Kconfig
>> +++ b/drivers/pci/Kconfig
>> @@ -374,4 +374,13 @@ config PCIE_UNIPHIER
>> Say Y here if you want to enable PCIe controller support on
>> UniPhier SoCs.
>>
>> +config PCIE_STARFIVE_JH7110
>> + bool "Enable Starfive JH7110 PCIe driver"
>> + imply STARFIVE_JH7110
>> + imply CLK_JH7110
>> + imply RESET_JH7110
>> + help
>> + Say Y here if you want to enable PCIe controller support on
>> + StarFive JH7110 SoC.
>> +
>> endif
>> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
>> index 49506e7ba5..bbe3323bb5 100644
>> --- a/drivers/pci/Makefile
>> +++ b/drivers/pci/Makefile
>> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
>> obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
>> obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
>> obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
>> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
>> diff --git a/drivers/pci/pcie_starfive_jh7110.c
>> b/drivers/pci/pcie_starfive_jh7110.c
>> new file mode 100644
>> index 00..130181013e
>> --- /dev/null
>> +++ b/drivers/pci/pcie_starfive_jh7110.c
>> @@ -0,0 +1,465 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * StarFive PLDA PCIe host controller driver
>> + *
>> + * Copyright (c) 2023 Starfive, Inc.
>> + * Author: Mason Huo
>> + *
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#define GEN_SETTINGS 0x80
>> +#define PCIE_PCI_IDS 0x9C
>> +#define PCIE_WINROM0xFC
>> +#define PMSG_SUPPORT_RX0x3F0
>> +#define PCI_MISC 0xB4
>> +
>> +#define PLDA_EP_ENABLE 0
>> +#define PLDA_RP_ENABLE 1
>> +
>> +#define IDS_CLASS_CODE_SHIFT 8
>> +
>> +#define PREF_MEM_WIN_64_SUPPORTBIT(3)
>> +#define PMSG_LTR_SUPPORT BIT(2)
>> +#define PLDA_FUNCTION_DIS BIT(15)
>> +#define PLDA_FUNC_NUM 4
>> +#define PLDA_PHY_FUNC_SHIFT9
>> +
>> +#define XR3PCI_ATR_AXI4_SLV0 0x800
>> +#define XR3PCI_ATR_SRC_ADDR_LOW0x0
>> +#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
>> +#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
>> +#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
>> +#define XR3PCI_ATR_TRSL_PARAM 0x10
>> +#define XR3PCI_ATR_TABLE_OFFSET0x20
>> +#define XR3PCI_ATR_MAX_TABLE_NUM 8
>> +
>> +#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
>> +#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12)
>> +#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12)
>> +#define XR3_PCI_ECAM_SIZE 28
>> +#define XR3PCI_ATR_TRSL_DIRBIT(22)
>> +/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
>> +#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
>> +#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
>> +
>> +/* system control */
>> +#define STG_SYSCON_K_RP_NEP_MASK BIT(8)
>> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8)
>> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8
>> +#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0)
>> +#define STG_SYSCON_CLKREQ_MASK BIT(22)
>> +#define STG_SYSCON_CKREF_SRC_SHIFT 18
>> +#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18)
>> +
>> +struct starfive_pcie {
>> + struct udevice *dev;
>> +
>> + void __iomem *reg_base;
>> + void __iomem *cfg_base;
>> +
>> + struct regmap *regmap;
>> + u32 stg_arfun;
>> + u32 stg_awfun;
>> + u32 stg_rp_nep;
>> +
>> + struct clk_bulk clks;
>> + struct reset_ctl_bulk rsts;
>> + struct gpio_descreset_gpio;
>> +
>> + int atr_table_num;
>> + int sec_busno;
>> +};
>> +
>> +static bool starfive_pcie_addr_valid(pci_dev_t bdf, struct starfive_pcie
>> *priv)
>> +{
>> + /*
>> +* Single device limitation.
>> +* For JH7110 SoC limitation, one
Re: [PATCH v4 1/3] starfive: pci: Add StarFive JH7110 pcie driver
On Tue, Apr 11, 2023 at 9:03 AM Minda Chen wrote:
>
> From: Mason Huo
>
> Add pcie driver for StarFive JH7110, the driver depends on
> starfive gpio, pinctrl, clk and reset driver to do init.
>
> Several devices are tested:
> a) M.2 NVMe SSD
> b) Realtek 8169 Ethernet adapter.
>
> Signed-off-by: Mason Huo
> Signed-off-by: Minda Chen
> ---
> drivers/pci/Kconfig| 9 +
> drivers/pci/Makefile | 1 +
> drivers/pci/pcie_starfive_jh7110.c | 465 +
> 3 files changed, 475 insertions(+)
> create mode 100644 drivers/pci/pcie_starfive_jh7110.c
>
> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> index ef328d2652..f37b6baa25 100644
> --- a/drivers/pci/Kconfig
> +++ b/drivers/pci/Kconfig
> @@ -374,4 +374,13 @@ config PCIE_UNIPHIER
> Say Y here if you want to enable PCIe controller support on
> UniPhier SoCs.
>
> +config PCIE_STARFIVE_JH7110
> + bool "Enable Starfive JH7110 PCIe driver"
> + imply STARFIVE_JH7110
> + imply CLK_JH7110
> + imply RESET_JH7110
> + help
> + Say Y here if you want to enable PCIe controller support on
> + StarFive JH7110 SoC.
> +
> endif
> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> index 49506e7ba5..bbe3323bb5 100644
> --- a/drivers/pci/Makefile
> +++ b/drivers/pci/Makefile
> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
> obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
> obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
> obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
> diff --git a/drivers/pci/pcie_starfive_jh7110.c
> b/drivers/pci/pcie_starfive_jh7110.c
> new file mode 100644
> index 00..130181013e
> --- /dev/null
> +++ b/drivers/pci/pcie_starfive_jh7110.c
> @@ -0,0 +1,465 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * StarFive PLDA PCIe host controller driver
> + *
> + * Copyright (c) 2023 Starfive, Inc.
> + * Author: Mason Huo
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define GEN_SETTINGS 0x80
> +#define PCIE_PCI_IDS 0x9C
> +#define PCIE_WINROM0xFC
> +#define PMSG_SUPPORT_RX0x3F0
> +#define PCI_MISC 0xB4
> +
> +#define PLDA_EP_ENABLE 0
> +#define PLDA_RP_ENABLE 1
> +
> +#define IDS_CLASS_CODE_SHIFT 8
> +
> +#define PREF_MEM_WIN_64_SUPPORTBIT(3)
> +#define PMSG_LTR_SUPPORT BIT(2)
> +#define PLDA_FUNCTION_DIS BIT(15)
> +#define PLDA_FUNC_NUM 4
> +#define PLDA_PHY_FUNC_SHIFT9
> +
> +#define XR3PCI_ATR_AXI4_SLV0 0x800
> +#define XR3PCI_ATR_SRC_ADDR_LOW0x0
> +#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
> +#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
> +#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
> +#define XR3PCI_ATR_TRSL_PARAM 0x10
> +#define XR3PCI_ATR_TABLE_OFFSET0x20
> +#define XR3PCI_ATR_MAX_TABLE_NUM 8
> +
> +#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
> +#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12)
> +#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12)
> +#define XR3_PCI_ECAM_SIZE 28
> +#define XR3PCI_ATR_TRSL_DIRBIT(22)
> +/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
> +#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
> +#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
> +
> +/* system control */
> +#define STG_SYSCON_K_RP_NEP_MASK BIT(8)
> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8)
> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8
> +#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0)
> +#define STG_SYSCON_CLKREQ_MASK BIT(22)
> +#define STG_SYSCON_CKREF_SRC_SHIFT 18
> +#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18)
> +
> +struct starfive_pcie {
> + struct udevice *dev;
> +
> + void __iomem *reg_base;
> + void __iomem *cfg_base;
> +
> + struct regmap *regmap;
> + u32 stg_arfun;
> + u32 stg_awfun;
> + u32 stg_rp_nep;
> +
> + struct clk_bulk clks;
> + struct reset_ctl_bulk rsts;
> + struct gpio_descreset_gpio;
> +
> + int atr_table_num;
> + int sec_busno;
> +};
> +
> +static bool starfive_pcie_addr_valid(pci_dev_t bdf, struct starfive_pcie
> *priv)
> +{
> + /*
> +* Single device limitation.
> +* For JH7110 SoC limitation, one bus can only connnect one device.
> +* And PCIe controller contain HW issue that secondary bus of
> +* host bridge emumerate duplicate devices.
> +* Only can access device
[PATCH v4 1/3] starfive: pci: Add StarFive JH7110 pcie driver
From: Mason Huo
Add pcie driver for StarFive JH7110, the driver depends on
starfive gpio, pinctrl, clk and reset driver to do init.
Several devices are tested:
a) M.2 NVMe SSD
b) Realtek 8169 Ethernet adapter.
Signed-off-by: Mason Huo
Signed-off-by: Minda Chen
---
drivers/pci/Kconfig| 9 +
drivers/pci/Makefile | 1 +
drivers/pci/pcie_starfive_jh7110.c | 465 +
3 files changed, 475 insertions(+)
create mode 100644 drivers/pci/pcie_starfive_jh7110.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ef328d2652..f37b6baa25 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -374,4 +374,13 @@ config PCIE_UNIPHIER
Say Y here if you want to enable PCIe controller support on
UniPhier SoCs.
+config PCIE_STARFIVE_JH7110
+ bool "Enable Starfive JH7110 PCIe driver"
+ imply STARFIVE_JH7110
+ imply CLK_JH7110
+ imply RESET_JH7110
+ help
+ Say Y here if you want to enable PCIe controller support on
+ StarFive JH7110 SoC.
+
endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 49506e7ba5..bbe3323bb5 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
+obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
diff --git a/drivers/pci/pcie_starfive_jh7110.c
b/drivers/pci/pcie_starfive_jh7110.c
new file mode 100644
index 00..130181013e
--- /dev/null
+++ b/drivers/pci/pcie_starfive_jh7110.c
@@ -0,0 +1,465 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive PLDA PCIe host controller driver
+ *
+ * Copyright (c) 2023 Starfive, Inc.
+ * Author: Mason Huo
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GEN_SETTINGS 0x80
+#define PCIE_PCI_IDS 0x9C
+#define PCIE_WINROM0xFC
+#define PMSG_SUPPORT_RX0x3F0
+#define PCI_MISC 0xB4
+
+#define PLDA_EP_ENABLE 0
+#define PLDA_RP_ENABLE 1
+
+#define IDS_CLASS_CODE_SHIFT 8
+
+#define PREF_MEM_WIN_64_SUPPORTBIT(3)
+#define PMSG_LTR_SUPPORT BIT(2)
+#define PLDA_FUNCTION_DIS BIT(15)
+#define PLDA_FUNC_NUM 4
+#define PLDA_PHY_FUNC_SHIFT9
+
+#define XR3PCI_ATR_AXI4_SLV0 0x800
+#define XR3PCI_ATR_SRC_ADDR_LOW0x0
+#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
+#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
+#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
+#define XR3PCI_ATR_TRSL_PARAM 0x10
+#define XR3PCI_ATR_TABLE_OFFSET0x20
+#define XR3PCI_ATR_MAX_TABLE_NUM 8
+
+#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
+#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12)
+#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12)
+#define XR3_PCI_ECAM_SIZE 28
+#define XR3PCI_ATR_TRSL_DIRBIT(22)
+/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
+#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
+#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
+
+/* system control */
+#define STG_SYSCON_K_RP_NEP_MASK BIT(8)
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8)
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8
+#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0)
+#define STG_SYSCON_CLKREQ_MASK BIT(22)
+#define STG_SYSCON_CKREF_SRC_SHIFT 18
+#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18)
+
+struct starfive_pcie {
+ struct udevice *dev;
+
+ void __iomem *reg_base;
+ void __iomem *cfg_base;
+
+ struct regmap *regmap;
+ u32 stg_arfun;
+ u32 stg_awfun;
+ u32 stg_rp_nep;
+
+ struct clk_bulk clks;
+ struct reset_ctl_bulk rsts;
+ struct gpio_descreset_gpio;
+
+ int atr_table_num;
+ int sec_busno;
+};
+
+static bool starfive_pcie_addr_valid(pci_dev_t bdf, struct starfive_pcie *priv)
+{
+ /*
+* Single device limitation.
+* For JH7110 SoC limitation, one bus can only connnect one device.
+* And PCIe controller contain HW issue that secondary bus of
+* host bridge emumerate duplicate devices.
+* Only can access device 0 in secondary bus.
+*/
+ if (PCI_BUS(bdf) == priv->sec_busno && PCI_DEV(bdf) > 0)
+ return false;
+
+ return true;
+}
+
+static int starfive_pcie_conf_address(const struct udevice *udev, pci_dev_t
bdf,
+ uint offset, void **paddr)
+{
+ struct starfive_pcie *priv =
