Re: [PATCH v4 1/5] arm: x86: qemu: move qfw to DM uclass, add Arm support
Hi Asherah,
On Wed, Feb 24, 2021 at 11:23 AM Asherah Connor wrote:
>
> Updates the QFW driver to use the driver model, splitting the driver
> into qfw_pio and qfw_mmio (for non-x86) in their own uclass.
>
> Signed-off-by: Asherah Connor
> ---
>
> Changes in v4:
> - PIO definitions are now #defines
> - qfw_*_plat structs are no longer in header files
> - Remove yield/pause in DMA wait loop
> - Change struct udevice *qfw_get_dev(void) to int qfw_get_dev(struct
> udevice **)
>
> arch/arm/Kconfig | 1 +
> arch/x86/cpu/qemu/cpu.c | 9 +-
> arch/x86/cpu/qemu/qemu.c | 47 +---
> arch/x86/cpu/qfw_cpu.c | 11 +-
> cmd/qfw.c| 52 -
> common/Makefile | 2 +
> common/qfw.c | 105 +
> drivers/misc/Makefile| 6 +-
> drivers/misc/qfw.c | 238 ++-
> drivers/misc/qfw_mmio.c | 119
> drivers/misc/qfw_pio.c | 69
> include/dm/uclass-id.h | 1 +
> include/qfw.h| 61 ++
> 13 files changed, 466 insertions(+), 255 deletions(-)
> create mode 100644 common/qfw.c
> create mode 100644 drivers/misc/qfw_mmio.c
> create mode 100644 drivers/misc/qfw_pio.c
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index d51abbeaf0..cd01dc458a 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -937,6 +937,7 @@ config ARCH_QEMU
> imply DM_RNG
> imply DM_RTC
> imply RTC_PL031
> + imply CMD_QFW
>
> config ARCH_RMOBILE
> bool "Renesas ARM SoCs"
> diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c
> index 9ce86b379c..c78e374644 100644
> --- a/arch/x86/cpu/qemu/cpu.c
> +++ b/arch/x86/cpu/qemu/cpu.c
> @@ -22,7 +22,14 @@ int cpu_qemu_get_desc(const struct udevice *dev, char
> *buf, int size)
>
> static int cpu_qemu_get_count(const struct udevice *dev)
> {
> - return qemu_fwcfg_online_cpus();
> + int ret;
> + struct udevice *qfw_dev;
> +
> + ret = qfw_get_dev(_dev);
> + if (ret)
> + return ret;
> +
> + return qemu_fwcfg_online_cpus(qfw_dev);
> }
>
> static const struct cpu_ops cpu_qemu_ops = {
> diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
> index 044a429c13..605f51e1b8 100644
> --- a/arch/x86/cpu/qemu/qemu.c
> +++ b/arch/x86/cpu/qemu/qemu.c
> @@ -8,6 +8,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -18,46 +19,10 @@ static bool i440fx;
>
> #ifdef CONFIG_QFW
>
> -/* on x86, the qfw registers are all IO ports */
> -#define FW_CONTROL_PORT0x510
> -#define FW_DATA_PORT 0x511
> -#define FW_DMA_PORT_LOW0x514
> -#define FW_DMA_PORT_HIGH 0x518
> -
> -static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry,
> - uint32_t size, void *address)
> -{
> - uint32_t i = 0;
> - uint8_t *data = address;
> -
> - /*
> -* writting FW_CFG_INVALID will cause read operation to resume at
> -* last offset, otherwise read will start at offset 0
> -*
> -* Note: on platform where the control register is IO port, the
> -* endianness is little endian.
> -*/
> - if (entry != FW_CFG_INVALID)
> - outw(cpu_to_le16(entry), FW_CONTROL_PORT);
> -
> - /* the endianness of data register is string-preserving */
> - while (size--)
> - data[i++] = inb(FW_DATA_PORT);
> -}
> -
> -static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma)
> -{
> - /* the DMA address register is big endian */
> - outl(cpu_to_be32((uintptr_t)dma), FW_DMA_PORT_HIGH);
> -
> - while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR)
> - __asm__ __volatile__ ("pause");
> -}
> -
> -static struct fw_cfg_arch_ops fwcfg_x86_ops = {
> - .arch_read_pio = qemu_x86_fwcfg_read_entry_pio,
> - .arch_read_dma = qemu_x86_fwcfg_read_entry_dma
> +U_BOOT_DRVINFO(x86_qfw_pio) = {
> + .name = "qfw_pio",
> };
> +
> #endif
>
> static void enable_pm_piix(void)
> @@ -132,10 +97,6 @@ static void qemu_chipset_init(void)
>
> enable_pm_ich9();
> }
> -
> -#ifdef CONFIG_QFW
> - qemu_fwcfg_init(_x86_ops);
> -#endif
> }
>
> #if !CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT)
> diff --git a/arch/x86/cpu/qfw_cpu.c b/arch/x86/cpu/qfw_cpu.c
> index b959eaddde..9700908064 100644
> --- a/arch/x86/cpu/qfw_cpu.c
> +++ b/arch/x86/cpu/qfw_cpu.c
> @@ -18,7 +18,7 @@ int qemu_cpu_fixup(void)
> int cpu_num;
> int cpu_online;
> struct uclass *uc;
> - struct udevice *dev, *pdev;
> + struct udevice *dev, *pdev, *qfwdev;
> struct cpu_plat *plat;
> char *cpu;
>
> @@ -39,6 +39,13 @@ int qemu_cpu_fixup(void)
> return -ENODEV;
> }
>
> + /* get qfw dev */
> + ret = qfw_get_dev();
> + if (ret) {
> + printf("unable to find qfw
Re: [PATCH v4 1/5] arm: x86: qemu: move qfw to DM uclass, add Arm support
Hi Bin, On 21/02/26 10:02:p, Bin Meng wrote: > On Fri, Feb 26, 2021 at 10:14 AM Bin Meng wrote: > > This patch mixed two things together. The adding ARM support should > > not belong to this patch. > > So we need to split the patch like this: > > 1. Convert the existing QFW driver of x86 to QFW uclass driver > 2. Add a new QFW mmio driver > 3. Enable the driver on QEMU ARM Thanks for taking a look! I'll redo the series accordingly. Best, Asherah
Re: [PATCH v4 1/5] arm: x86: qemu: move qfw to DM uclass, add Arm support
Hi Asherah, On Fri, Feb 26, 2021 at 10:14 AM Bin Meng wrote: > > Hi Asherah, > > On Wed, Feb 24, 2021 at 11:23 AM Asherah Connor wrote: > > > > Updates the QFW driver to use the driver model, splitting the driver > > into qfw_pio and qfw_mmio (for non-x86) in their own uclass. > > > > Signed-off-by: Asherah Connor > > --- > > > > Changes in v4: > > - PIO definitions are now #defines > > - qfw_*_plat structs are no longer in header files > > - Remove yield/pause in DMA wait loop > > - Change struct udevice *qfw_get_dev(void) to int qfw_get_dev(struct > > udevice **) > > > > arch/arm/Kconfig | 1 + > > arch/x86/cpu/qemu/cpu.c | 9 +- > > arch/x86/cpu/qemu/qemu.c | 47 +--- > > arch/x86/cpu/qfw_cpu.c | 11 +- > > cmd/qfw.c| 52 - > > common/Makefile | 2 + > > common/qfw.c | 105 + > > drivers/misc/Makefile| 6 +- > > drivers/misc/qfw.c | 238 ++- > > drivers/misc/qfw_mmio.c | 119 > > drivers/misc/qfw_pio.c | 69 > > include/dm/uclass-id.h | 1 + > > include/qfw.h| 61 ++ > > 13 files changed, 466 insertions(+), 255 deletions(-) > > create mode 100644 common/qfw.c > > create mode 100644 drivers/misc/qfw_mmio.c > > create mode 100644 drivers/misc/qfw_pio.c > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > index d51abbeaf0..cd01dc458a 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -937,6 +937,7 @@ config ARCH_QEMU > > imply DM_RNG > > imply DM_RTC > > imply RTC_PL031 > > + imply CMD_QFW > > This patch mixed two things together. The adding ARM support should > not belong to this patch. So we need to split the patch like this: 1. Convert the existing QFW driver of x86 to QFW uclass driver 2. Add a new QFW mmio driver 3. Enable the driver on QEMU ARM Regards, Bin
Re: [PATCH v4 1/5] arm: x86: qemu: move qfw to DM uclass, add Arm support
Hi Asherah, On Wed, Feb 24, 2021 at 11:23 AM Asherah Connor wrote: > > Updates the QFW driver to use the driver model, splitting the driver > into qfw_pio and qfw_mmio (for non-x86) in their own uclass. > > Signed-off-by: Asherah Connor > --- > > Changes in v4: > - PIO definitions are now #defines > - qfw_*_plat structs are no longer in header files > - Remove yield/pause in DMA wait loop > - Change struct udevice *qfw_get_dev(void) to int qfw_get_dev(struct > udevice **) > > arch/arm/Kconfig | 1 + > arch/x86/cpu/qemu/cpu.c | 9 +- > arch/x86/cpu/qemu/qemu.c | 47 +--- > arch/x86/cpu/qfw_cpu.c | 11 +- > cmd/qfw.c| 52 - > common/Makefile | 2 + > common/qfw.c | 105 + > drivers/misc/Makefile| 6 +- > drivers/misc/qfw.c | 238 ++- > drivers/misc/qfw_mmio.c | 119 > drivers/misc/qfw_pio.c | 69 > include/dm/uclass-id.h | 1 + > include/qfw.h| 61 ++ > 13 files changed, 466 insertions(+), 255 deletions(-) > create mode 100644 common/qfw.c > create mode 100644 drivers/misc/qfw_mmio.c > create mode 100644 drivers/misc/qfw_pio.c > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index d51abbeaf0..cd01dc458a 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -937,6 +937,7 @@ config ARCH_QEMU > imply DM_RNG > imply DM_RTC > imply RTC_PL031 > + imply CMD_QFW This patch mixed two things together. The adding ARM support should not belong to this patch. > > config ARCH_RMOBILE > bool "Renesas ARM SoCs" > diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c > index 9ce86b379c..c78e374644 100644 Regards, Bin
Re: [PATCH v4 1/5] arm: x86: qemu: move qfw to DM uclass, add Arm support
On Tue, 23 Feb 2021 at 22:24, Asherah Connor wrote: > > Updates the QFW driver to use the driver model, splitting the driver > into qfw_pio and qfw_mmio (for non-x86) in their own uclass. > > Signed-off-by: Asherah Connor > --- > > Changes in v4: > - PIO definitions are now #defines > - qfw_*_plat structs are no longer in header files > - Remove yield/pause in DMA wait loop > - Change struct udevice *qfw_get_dev(void) to int qfw_get_dev(struct > udevice **) > > arch/arm/Kconfig | 1 + > arch/x86/cpu/qemu/cpu.c | 9 +- > arch/x86/cpu/qemu/qemu.c | 47 +--- > arch/x86/cpu/qfw_cpu.c | 11 +- > cmd/qfw.c| 52 - > common/Makefile | 2 + > common/qfw.c | 105 + > drivers/misc/Makefile| 6 +- > drivers/misc/qfw.c | 238 ++- > drivers/misc/qfw_mmio.c | 119 > drivers/misc/qfw_pio.c | 69 > include/dm/uclass-id.h | 1 + > include/qfw.h| 61 ++ > 13 files changed, 466 insertions(+), 255 deletions(-) > create mode 100644 common/qfw.c > create mode 100644 drivers/misc/qfw_mmio.c > create mode 100644 drivers/misc/qfw_pio.c Reviewed-by: Simon Glass
[PATCH v4 1/5] arm: x86: qemu: move qfw to DM uclass, add Arm support
Updates the QFW driver to use the driver model, splitting the driver
into qfw_pio and qfw_mmio (for non-x86) in their own uclass.
Signed-off-by: Asherah Connor
---
Changes in v4:
- PIO definitions are now #defines
- qfw_*_plat structs are no longer in header files
- Remove yield/pause in DMA wait loop
- Change struct udevice *qfw_get_dev(void) to int qfw_get_dev(struct
udevice **)
arch/arm/Kconfig | 1 +
arch/x86/cpu/qemu/cpu.c | 9 +-
arch/x86/cpu/qemu/qemu.c | 47 +---
arch/x86/cpu/qfw_cpu.c | 11 +-
cmd/qfw.c| 52 -
common/Makefile | 2 +
common/qfw.c | 105 +
drivers/misc/Makefile| 6 +-
drivers/misc/qfw.c | 238 ++-
drivers/misc/qfw_mmio.c | 119
drivers/misc/qfw_pio.c | 69
include/dm/uclass-id.h | 1 +
include/qfw.h| 61 ++
13 files changed, 466 insertions(+), 255 deletions(-)
create mode 100644 common/qfw.c
create mode 100644 drivers/misc/qfw_mmio.c
create mode 100644 drivers/misc/qfw_pio.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d51abbeaf0..cd01dc458a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -937,6 +937,7 @@ config ARCH_QEMU
imply DM_RNG
imply DM_RTC
imply RTC_PL031
+ imply CMD_QFW
config ARCH_RMOBILE
bool "Renesas ARM SoCs"
diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c
index 9ce86b379c..c78e374644 100644
--- a/arch/x86/cpu/qemu/cpu.c
+++ b/arch/x86/cpu/qemu/cpu.c
@@ -22,7 +22,14 @@ int cpu_qemu_get_desc(const struct udevice *dev, char *buf,
int size)
static int cpu_qemu_get_count(const struct udevice *dev)
{
- return qemu_fwcfg_online_cpus();
+ int ret;
+ struct udevice *qfw_dev;
+
+ ret = qfw_get_dev(_dev);
+ if (ret)
+ return ret;
+
+ return qemu_fwcfg_online_cpus(qfw_dev);
}
static const struct cpu_ops cpu_qemu_ops = {
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 044a429c13..605f51e1b8 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -18,46 +19,10 @@ static bool i440fx;
#ifdef CONFIG_QFW
-/* on x86, the qfw registers are all IO ports */
-#define FW_CONTROL_PORT0x510
-#define FW_DATA_PORT 0x511
-#define FW_DMA_PORT_LOW0x514
-#define FW_DMA_PORT_HIGH 0x518
-
-static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry,
- uint32_t size, void *address)
-{
- uint32_t i = 0;
- uint8_t *data = address;
-
- /*
-* writting FW_CFG_INVALID will cause read operation to resume at
-* last offset, otherwise read will start at offset 0
-*
-* Note: on platform where the control register is IO port, the
-* endianness is little endian.
-*/
- if (entry != FW_CFG_INVALID)
- outw(cpu_to_le16(entry), FW_CONTROL_PORT);
-
- /* the endianness of data register is string-preserving */
- while (size--)
- data[i++] = inb(FW_DATA_PORT);
-}
-
-static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma)
-{
- /* the DMA address register is big endian */
- outl(cpu_to_be32((uintptr_t)dma), FW_DMA_PORT_HIGH);
-
- while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR)
- __asm__ __volatile__ ("pause");
-}
-
-static struct fw_cfg_arch_ops fwcfg_x86_ops = {
- .arch_read_pio = qemu_x86_fwcfg_read_entry_pio,
- .arch_read_dma = qemu_x86_fwcfg_read_entry_dma
+U_BOOT_DRVINFO(x86_qfw_pio) = {
+ .name = "qfw_pio",
};
+
#endif
static void enable_pm_piix(void)
@@ -132,10 +97,6 @@ static void qemu_chipset_init(void)
enable_pm_ich9();
}
-
-#ifdef CONFIG_QFW
- qemu_fwcfg_init(_x86_ops);
-#endif
}
#if !CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT)
diff --git a/arch/x86/cpu/qfw_cpu.c b/arch/x86/cpu/qfw_cpu.c
index b959eaddde..9700908064 100644
--- a/arch/x86/cpu/qfw_cpu.c
+++ b/arch/x86/cpu/qfw_cpu.c
@@ -18,7 +18,7 @@ int qemu_cpu_fixup(void)
int cpu_num;
int cpu_online;
struct uclass *uc;
- struct udevice *dev, *pdev;
+ struct udevice *dev, *pdev, *qfwdev;
struct cpu_plat *plat;
char *cpu;
@@ -39,6 +39,13 @@ int qemu_cpu_fixup(void)
return -ENODEV;
}
+ /* get qfw dev */
+ ret = qfw_get_dev();
+ if (ret) {
+ printf("unable to find qfw device\n");
+ return ret;
+ }
+
/* calculate cpus that are already bound */
cpu_num = 0;
for (uclass_find_first_device(UCLASS_CPU, );
@@ -48,7 +55,7 @@ int qemu_cpu_fixup(void)
}
/* get actual cpu number */
- cpu_online = qemu_fwcfg_online_cpus();
+ cpu_online = qemu_fwcfg_online_cpus(qfwdev);
