Re: [PATCH v4 3/6] riscv: Provide a mechanism to fix DT for reserved memory
On Mon, Mar 23, 2020 at 11:14 PM Heinrich Schuchardt wrote:
>
> On 3/24/20 5:16 AM, Atish Patra wrote:
> > In RISC-V, M-mode software can reserve physical memory regions
> > by setting appropriate physical memory protection (PMP) csr. As the
> > PMP csr are accessible only in M-mode, S-mode U-Boot can not read
> > this configuration directly. However, M-mode software can pass this
> > information via reserved-memory node in device tree so that S-mode
> > software can access this information.
> >
> > This patch provides a framework to copy to the reserved-memory node
> > from one DT to another. This will be used to update the DT used by
> > U-Boot and the DT passed to the next stage OS.
> >
> > Signed-off-by: Atish Patra
> > ---
> > arch/riscv/cpu/start.S| 1 +
> > arch/riscv/include/asm/global_data.h | 1 +
> > arch/riscv/include/asm/u-boot-riscv.h | 2 +
> > arch/riscv/lib/Makefile | 1 +
> > arch/riscv/lib/asm-offsets.c | 1 +
> > arch/riscv/lib/fdt_fixup.c| 80 +++
> > 6 files changed, 86 insertions(+)
> > create mode 100644 arch/riscv/lib/fdt_fixup.c
> >
> > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> > index 6b3ff99c3882..0282685c2906 100644
> > --- a/arch/riscv/cpu/start.S
> > +++ b/arch/riscv/cpu/start.S
> > @@ -121,6 +121,7 @@ call_board_init_f_0:
> >
> > jal board_init_f_init_reserve
> >
> > + SREGs1, GD_FIRMWARE_FDT_ADDR(gp)
> > /* save the boot hart id to global_data */
> > SREGtp, GD_BOOT_HART(gp)
> >
> > diff --git a/arch/riscv/include/asm/global_data.h
> > b/arch/riscv/include/asm/global_data.h
> > index b74bd7e738bb..51ac8d1c98e2 100644
> > --- a/arch/riscv/include/asm/global_data.h
> > +++ b/arch/riscv/include/asm/global_data.h
> > @@ -15,6 +15,7 @@
> > /* Architecture-specific global data */
> > struct arch_global_data {
> > long boot_hart; /* boot hart id */
> > + phys_addr_t firmware_fdt_addr;
> > #ifdef CONFIG_SIFIVE_CLINT
> > void __iomem *clint;/* clint base address */
> > #endif
> > diff --git a/arch/riscv/include/asm/u-boot-riscv.h
> > b/arch/riscv/include/asm/u-boot-riscv.h
> > index 49febd588102..543a1688db8f 100644
> > --- a/arch/riscv/include/asm/u-boot-riscv.h
> > +++ b/arch/riscv/include/asm/u-boot-riscv.h
> > @@ -17,5 +17,7 @@ int cleanup_before_linux(void);
> > /* board/.../... */
> > int board_init(void);
> > void board_quiesce_devices(void);
> > +int riscv_board_reserved_mem_fixup(void *fdt);
> > +int riscv_fdt_copy_resv_mem_node(const void *src_fdt, void *dest_fdt);
> >
> > #endif /* _U_BOOT_RISCV_H_ */
> > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > index adadbf4bcbef..d132b59ce32c 100644
> > --- a/arch/riscv/lib/Makefile
> > +++ b/arch/riscv/lib/Makefile
> > @@ -24,6 +24,7 @@ obj-y += reset.o
> > obj-y += setjmp.o
> > obj-$(CONFIG_SMP) += smp.o
> > obj-$(CONFIG_SPL_BUILD) += spl.o
> > +obj-y += fdt_fixup.o
> >
> > # For building EFI apps
> > CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI)
> > diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
> > index 4fa4fd371473..7301c1b98e23 100644
> > --- a/arch/riscv/lib/asm-offsets.c
> > +++ b/arch/riscv/lib/asm-offsets.c
> > @@ -14,6 +14,7 @@
> > int main(void)
> > {
> > DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
> > + DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr));
> > #ifndef CONFIG_XIP
> > DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
> > #endif
> > diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c
> > new file mode 100644
> > index ..f3d1ec5c5d02
> > --- /dev/null
> > +++ b/arch/riscv/lib/fdt_fixup.c
> > @@ -0,0 +1,80 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (c) 2020 Western Digital Corporation or its affiliates
> > + *
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
>
> Please, provide Sphinx style comments for new functions. Cf.
> https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html.
>
Sure. I will do that.
> > +int riscv_fdt_copy_resv_mem_node(const void *src, void *dst)
> > +{
> > + u32 phandle;
> > + struct fdt_memory pmp_mem;
> > + fdt_addr_t addr;
> > + fdt_size_t size;
> > + int offset, node, err, rmem_offset;
> > + bool nomap = true;
> > + char basename[32] = {0};
> > + int bname_len;
> > + int max_len = sizeof(basename);
> > + const char *name;
> > + char *temp;
> > +
> > + offset = fdt_path_offset(src, "/reserved-memory");
> > + if (offset < 0) {
> > + printf("No reserved memory region found in source FDT\n");
> > + return 0;
> > + }
> > +
> > + fdt_for_each_subnode(node, src, offset) {
> > + name = fdt_get_name(src, node, NULL);
> > +
> > + addr =
Re: [PATCH v4 3/6] riscv: Provide a mechanism to fix DT for reserved memory
On 3/24/20 5:16 AM, Atish Patra wrote:
In RISC-V, M-mode software can reserve physical memory regions
by setting appropriate physical memory protection (PMP) csr. As the
PMP csr are accessible only in M-mode, S-mode U-Boot can not read
this configuration directly. However, M-mode software can pass this
information via reserved-memory node in device tree so that S-mode
software can access this information.
This patch provides a framework to copy to the reserved-memory node
from one DT to another. This will be used to update the DT used by
U-Boot and the DT passed to the next stage OS.
Signed-off-by: Atish Patra
---
arch/riscv/cpu/start.S| 1 +
arch/riscv/include/asm/global_data.h | 1 +
arch/riscv/include/asm/u-boot-riscv.h | 2 +
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/asm-offsets.c | 1 +
arch/riscv/lib/fdt_fixup.c| 80 +++
6 files changed, 86 insertions(+)
create mode 100644 arch/riscv/lib/fdt_fixup.c
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 6b3ff99c3882..0282685c2906 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -121,6 +121,7 @@ call_board_init_f_0:
jal board_init_f_init_reserve
+ SREGs1, GD_FIRMWARE_FDT_ADDR(gp)
/* save the boot hart id to global_data */
SREGtp, GD_BOOT_HART(gp)
diff --git a/arch/riscv/include/asm/global_data.h
b/arch/riscv/include/asm/global_data.h
index b74bd7e738bb..51ac8d1c98e2 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -15,6 +15,7 @@
/* Architecture-specific global data */
struct arch_global_data {
long boot_hart; /* boot hart id */
+ phys_addr_t firmware_fdt_addr;
#ifdef CONFIG_SIFIVE_CLINT
void __iomem *clint;/* clint base address */
#endif
diff --git a/arch/riscv/include/asm/u-boot-riscv.h
b/arch/riscv/include/asm/u-boot-riscv.h
index 49febd588102..543a1688db8f 100644
--- a/arch/riscv/include/asm/u-boot-riscv.h
+++ b/arch/riscv/include/asm/u-boot-riscv.h
@@ -17,5 +17,7 @@ int cleanup_before_linux(void);
/* board/.../... */
int board_init(void);
void board_quiesce_devices(void);
+int riscv_board_reserved_mem_fixup(void *fdt);
+int riscv_fdt_copy_resv_mem_node(const void *src_fdt, void *dest_fdt);
#endif/* _U_BOOT_RISCV_H_ */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index adadbf4bcbef..d132b59ce32c 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -24,6 +24,7 @@ obj-y += reset.o
obj-y += setjmp.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-y += fdt_fixup.o
# For building EFI apps
CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI)
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
index 4fa4fd371473..7301c1b98e23 100644
--- a/arch/riscv/lib/asm-offsets.c
+++ b/arch/riscv/lib/asm-offsets.c
@@ -14,6 +14,7 @@
int main(void)
{
DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
+ DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr));
#ifndef CONFIG_XIP
DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
#endif
diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c
new file mode 100644
index ..f3d1ec5c5d02
--- /dev/null
+++ b/arch/riscv/lib/fdt_fixup.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates
+ *
+ */
+
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
Please, provide Sphinx style comments for new functions. Cf.
https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html.
+int riscv_fdt_copy_resv_mem_node(const void *src, void *dst)
+{
+ u32 phandle;
+ struct fdt_memory pmp_mem;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int offset, node, err, rmem_offset;
+ bool nomap = true;
+ char basename[32] = {0};
+ int bname_len;
+ int max_len = sizeof(basename);
+ const char *name;
+ char *temp;
+
+ offset = fdt_path_offset(src, "/reserved-memory");
+ if (offset < 0) {
+ printf("No reserved memory region found in source FDT\n");
+ return 0;
+ }
+
+ fdt_for_each_subnode(node, src, offset) {
+ name = fdt_get_name(src, node, NULL);
+
+ addr = fdtdec_get_addr_size_auto_noparent(src, node,
+ "reg", 0, ,
+ false);
+ if (addr == FDT_ADDR_T_NONE) {
+ debug("failed to read address/size for %s\n", name);
+ continue;
+ }
+ strncpy(basename, name, max_len);
+ temp = strchr(basename, '@');
+ if (temp) {
+ bname_len = strnlen(basename,
[PATCH v4 3/6] riscv: Provide a mechanism to fix DT for reserved memory
In RISC-V, M-mode software can reserve physical memory regions
by setting appropriate physical memory protection (PMP) csr. As the
PMP csr are accessible only in M-mode, S-mode U-Boot can not read
this configuration directly. However, M-mode software can pass this
information via reserved-memory node in device tree so that S-mode
software can access this information.
This patch provides a framework to copy to the reserved-memory node
from one DT to another. This will be used to update the DT used by
U-Boot and the DT passed to the next stage OS.
Signed-off-by: Atish Patra
---
arch/riscv/cpu/start.S| 1 +
arch/riscv/include/asm/global_data.h | 1 +
arch/riscv/include/asm/u-boot-riscv.h | 2 +
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/asm-offsets.c | 1 +
arch/riscv/lib/fdt_fixup.c| 80 +++
6 files changed, 86 insertions(+)
create mode 100644 arch/riscv/lib/fdt_fixup.c
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 6b3ff99c3882..0282685c2906 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -121,6 +121,7 @@ call_board_init_f_0:
jal board_init_f_init_reserve
+ SREGs1, GD_FIRMWARE_FDT_ADDR(gp)
/* save the boot hart id to global_data */
SREGtp, GD_BOOT_HART(gp)
diff --git a/arch/riscv/include/asm/global_data.h
b/arch/riscv/include/asm/global_data.h
index b74bd7e738bb..51ac8d1c98e2 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -15,6 +15,7 @@
/* Architecture-specific global data */
struct arch_global_data {
long boot_hart; /* boot hart id */
+ phys_addr_t firmware_fdt_addr;
#ifdef CONFIG_SIFIVE_CLINT
void __iomem *clint;/* clint base address */
#endif
diff --git a/arch/riscv/include/asm/u-boot-riscv.h
b/arch/riscv/include/asm/u-boot-riscv.h
index 49febd588102..543a1688db8f 100644
--- a/arch/riscv/include/asm/u-boot-riscv.h
+++ b/arch/riscv/include/asm/u-boot-riscv.h
@@ -17,5 +17,7 @@ int cleanup_before_linux(void);
/* board/.../... */
int board_init(void);
void board_quiesce_devices(void);
+int riscv_board_reserved_mem_fixup(void *fdt);
+int riscv_fdt_copy_resv_mem_node(const void *src_fdt, void *dest_fdt);
#endif /* _U_BOOT_RISCV_H_ */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index adadbf4bcbef..d132b59ce32c 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -24,6 +24,7 @@ obj-y += reset.o
obj-y += setjmp.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_SPL_BUILD)+= spl.o
+obj-y += fdt_fixup.o
# For building EFI apps
CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI)
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
index 4fa4fd371473..7301c1b98e23 100644
--- a/arch/riscv/lib/asm-offsets.c
+++ b/arch/riscv/lib/asm-offsets.c
@@ -14,6 +14,7 @@
int main(void)
{
DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
+ DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr));
#ifndef CONFIG_XIP
DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
#endif
diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c
new file mode 100644
index ..f3d1ec5c5d02
--- /dev/null
+++ b/arch/riscv/lib/fdt_fixup.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates
+ *
+ */
+
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int riscv_fdt_copy_resv_mem_node(const void *src, void *dst)
+{
+ u32 phandle;
+ struct fdt_memory pmp_mem;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int offset, node, err, rmem_offset;
+ bool nomap = true;
+ char basename[32] = {0};
+ int bname_len;
+ int max_len = sizeof(basename);
+ const char *name;
+ char *temp;
+
+ offset = fdt_path_offset(src, "/reserved-memory");
+ if (offset < 0) {
+ printf("No reserved memory region found in source FDT\n");
+ return 0;
+ }
+
+ fdt_for_each_subnode(node, src, offset) {
+ name = fdt_get_name(src, node, NULL);
+
+ addr = fdtdec_get_addr_size_auto_noparent(src, node,
+ "reg", 0, ,
+ false);
+ if (addr == FDT_ADDR_T_NONE) {
+ debug("failed to read address/size for %s\n", name);
+ continue;
+ }
+ strncpy(basename, name, max_len);
+ temp = strchr(basename, '@');
+ if (temp) {
+ bname_len = strnlen(basename, max_len) - strnlen(temp,
+ max_len);
+ *(basename + bname_len) = '\0';
+ }
+
