Re: [PATCH v6 01/18] video: tegra20: dc: diverge DC per-SOC
пт, 19 квіт. 2024 р. о 19:26 Thierry Reding пише: > > On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > [...] > > diff --git a/arch/arm/include/asm/arch-tegra114/display.h > > b/arch/arm/include/asm/arch-tegra114/display.h > > new file mode 100644 > > index 00..9411525799 > > --- /dev/null > > +++ b/arch/arm/include/asm/arch-tegra114/display.h > > @@ -0,0 +1,28 @@ > > +/* SPDX-License-Identifier: GPL-2.0+ */ > > +/* > > + * (C) Copyright 2010 > > + * NVIDIA Corporation > > + */ > > + > > +#ifndef __ASM_ARCH_TEGRA_DISPLAY_H > > +#define __ASM_ARCH_TEGRA_DISPLAY_H > > + > > +#include > > + > > +/* This holds information about a window which can be displayed */ > > +struct disp_ctl_win { > > + enum win_color_depth_id fmt;/* Color depth/format */ > > + unsigned intbpp;/* Bits per pixel */ > > + phys_addr_t phys_addr; /* Physical address in memory */ > > + unsigned intx; /* Horizontal address offset (bytes) > > */ > > + unsigned inty; /* Veritical address offset (bytes) */ > > + unsigned intw; /* Width of source window */ > > + unsigned inth; /* Height of source window */ > > + unsigned intstride; /* Number of bytes per line */ > > + unsigned intout_x; /* Left edge of output window (col) */ > > + unsigned intout_y; /* Top edge of output window (row) */ > > + unsigned intout_w; /* Width of output window in pixels */ > > + unsigned intout_h; /* Height of output window in pixels > > */ > > +}; > > + > > +#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ > > One of the earlier patches in the series gets rid of this per-SoC header > file in favor of a common one. Did this end up here by mistake? It > doesn't seem to be used. > > > diff --git a/drivers/video/tegra20/tegra-dc.c > > b/drivers/video/tegra20/tegra-dc.c > > index f53ad46397..7605e77bc1 100644 > > --- a/drivers/video/tegra20/tegra-dc.c > > +++ b/drivers/video/tegra20/tegra-dc.c > > @@ -3,7 +3,6 @@ > > * Copyright (c) 2011 The Chromium OS Authors. > > */ > > > > -#include > > #include > > #include > > #include > > @@ -23,10 +22,15 @@ > > #include > > #include > > #include > > -#include > > > > DECLARE_GLOBAL_DATA_PTR; > > > > +/* Holder of Tegra per-SOC DC differences */ > > +struct tegra_dc_soc_info { > > + bool has_timer; > > + bool has_rgb; > > +}; > > + > > /* Information about the display controller */ > > struct tegra_lcd_priv { > > int width; /* width in pixels */ > > @@ -35,6 +39,7 @@ struct tegra_lcd_priv { > > struct display_timing timing; > > struct udevice *panel; > > struct dc_ctlr *dc; /* Display controller regmap */ > > + const struct tegra_dc_soc_info *soc; > > fdt_addr_t frame_buffer;/* Address of frame buffer */ > > unsigned pixel_clock; /* Pixel clock in Hz */ > > int dc_clk[2]; /* Contains clk and its parent */ > > @@ -43,8 +48,8 @@ struct tegra_lcd_priv { > > > > enum { > > /* Maximum LCD size we support */ > > - LCD_MAX_WIDTH = 1920, > > - LCD_MAX_HEIGHT = 1200, > > + LCD_MAX_WIDTH = 2560, > > + LCD_MAX_HEIGHT = 1600, > > LCD_MAX_LOG2_BPP= VIDEO_BPP16, > > }; > > > > @@ -110,9 +115,9 @@ static void update_window(struct tegra_lcd_priv *priv, > > writel(val, &dc->cmd.state_ctrl); > > } > > > > -static int update_display_mode(struct dc_disp_reg *disp, > > -struct tegra_lcd_priv *priv) > > +static int update_display_mode(struct tegra_lcd_priv *priv) > > { > > + struct dc_disp_reg *disp = &priv->dc->disp; > > struct display_timing *dt = &priv->timing; > > unsigned long val; > > unsigned long rate; > > @@ -128,14 +133,16 @@ static int update_display_mode(struct dc_disp_reg > > *disp, > > &disp->front_porch); > > writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active); > > > > - val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT; > > - val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT; > > - writel(val, &disp->data_enable_opt); > > + if (priv->soc->has_rgb) { > > + val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT; > > + val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT; > > + writel(val, &disp->data_enable_opt); > > > > - val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT; > > - val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT; > > - val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT; > > - writel(val, &disp->disp_interface_ctrl); > > + val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT; > > + val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT; > > + val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT; > > + writel(val, &disp->disp_interface_ctrl
Re: [PATCH v6 01/18] video: tegra20: dc: diverge DC per-SOC
On Fri Apr 19, 2024 at 6:26 PM CEST, Thierry Reding wrote: > On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > [...] > > diff --git a/arch/arm/include/asm/arch-tegra114/display.h > > b/arch/arm/include/asm/arch-tegra114/display.h > > new file mode 100644 > > index 00..9411525799 > > --- /dev/null > > +++ b/arch/arm/include/asm/arch-tegra114/display.h > > @@ -0,0 +1,28 @@ > > +/* SPDX-License-Identifier: GPL-2.0+ */ > > +/* > > + * (C) Copyright 2010 > > + * NVIDIA Corporation > > + */ > > + > > +#ifndef __ASM_ARCH_TEGRA_DISPLAY_H > > +#define __ASM_ARCH_TEGRA_DISPLAY_H > > + > > +#include > > + > > +/* This holds information about a window which can be displayed */ > > +struct disp_ctl_win { > > + enum win_color_depth_id fmt;/* Color depth/format */ > > + unsigned intbpp;/* Bits per pixel */ > > + phys_addr_t phys_addr; /* Physical address in memory */ > > + unsigned intx; /* Horizontal address offset (bytes) */ > > + unsigned inty; /* Veritical address offset (bytes) */ > > + unsigned intw; /* Width of source window */ > > + unsigned inth; /* Height of source window */ > > + unsigned intstride; /* Number of bytes per line */ > > + unsigned intout_x; /* Left edge of output window (col) */ > > + unsigned intout_y; /* Top edge of output window (row) */ > > + unsigned intout_w; /* Width of output window in pixels */ > > + unsigned intout_h; /* Height of output window in pixels */ > > +}; > > + > > +#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ > > One of the earlier patches in the series gets rid of this per-SoC header > file in favor of a common one. Did this end up here by mistake? It > doesn't seem to be used. Nevermind, my MUA sorted these patches weirdly, so it appeared as if this was later in the series than it actually was. Thierry signature.asc Description: PGP signature
Re: [PATCH v6 01/18] video: tegra20: dc: diverge DC per-SOC
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: [...] > diff --git a/arch/arm/include/asm/arch-tegra114/display.h > b/arch/arm/include/asm/arch-tegra114/display.h > new file mode 100644 > index 00..9411525799 > --- /dev/null > +++ b/arch/arm/include/asm/arch-tegra114/display.h > @@ -0,0 +1,28 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * (C) Copyright 2010 > + * NVIDIA Corporation > + */ > + > +#ifndef __ASM_ARCH_TEGRA_DISPLAY_H > +#define __ASM_ARCH_TEGRA_DISPLAY_H > + > +#include > + > +/* This holds information about a window which can be displayed */ > +struct disp_ctl_win { > + enum win_color_depth_id fmt;/* Color depth/format */ > + unsigned intbpp;/* Bits per pixel */ > + phys_addr_t phys_addr; /* Physical address in memory */ > + unsigned intx; /* Horizontal address offset (bytes) */ > + unsigned inty; /* Veritical address offset (bytes) */ > + unsigned intw; /* Width of source window */ > + unsigned inth; /* Height of source window */ > + unsigned intstride; /* Number of bytes per line */ > + unsigned intout_x; /* Left edge of output window (col) */ > + unsigned intout_y; /* Top edge of output window (row) */ > + unsigned intout_w; /* Width of output window in pixels */ > + unsigned intout_h; /* Height of output window in pixels */ > +}; > + > +#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ One of the earlier patches in the series gets rid of this per-SoC header file in favor of a common one. Did this end up here by mistake? It doesn't seem to be used. > diff --git a/drivers/video/tegra20/tegra-dc.c > b/drivers/video/tegra20/tegra-dc.c > index f53ad46397..7605e77bc1 100644 > --- a/drivers/video/tegra20/tegra-dc.c > +++ b/drivers/video/tegra20/tegra-dc.c > @@ -3,7 +3,6 @@ > * Copyright (c) 2011 The Chromium OS Authors. > */ > > -#include > #include > #include > #include > @@ -23,10 +22,15 @@ > #include > #include > #include > -#include > > DECLARE_GLOBAL_DATA_PTR; > > +/* Holder of Tegra per-SOC DC differences */ > +struct tegra_dc_soc_info { > + bool has_timer; > + bool has_rgb; > +}; > + > /* Information about the display controller */ > struct tegra_lcd_priv { > int width; /* width in pixels */ > @@ -35,6 +39,7 @@ struct tegra_lcd_priv { > struct display_timing timing; > struct udevice *panel; > struct dc_ctlr *dc; /* Display controller regmap */ > + const struct tegra_dc_soc_info *soc; > fdt_addr_t frame_buffer;/* Address of frame buffer */ > unsigned pixel_clock; /* Pixel clock in Hz */ > int dc_clk[2]; /* Contains clk and its parent */ > @@ -43,8 +48,8 @@ struct tegra_lcd_priv { > > enum { > /* Maximum LCD size we support */ > - LCD_MAX_WIDTH = 1920, > - LCD_MAX_HEIGHT = 1200, > + LCD_MAX_WIDTH = 2560, > + LCD_MAX_HEIGHT = 1600, > LCD_MAX_LOG2_BPP= VIDEO_BPP16, > }; > > @@ -110,9 +115,9 @@ static void update_window(struct tegra_lcd_priv *priv, > writel(val, &dc->cmd.state_ctrl); > } > > -static int update_display_mode(struct dc_disp_reg *disp, > -struct tegra_lcd_priv *priv) > +static int update_display_mode(struct tegra_lcd_priv *priv) > { > + struct dc_disp_reg *disp = &priv->dc->disp; > struct display_timing *dt = &priv->timing; > unsigned long val; > unsigned long rate; > @@ -128,14 +133,16 @@ static int update_display_mode(struct dc_disp_reg *disp, > &disp->front_porch); > writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active); > > - val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT; > - val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT; > - writel(val, &disp->data_enable_opt); > + if (priv->soc->has_rgb) { > + val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT; > + val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT; > + writel(val, &disp->data_enable_opt); > > - val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT; > - val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT; > - val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT; > - writel(val, &disp->disp_interface_ctrl); > + val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT; > + val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT; > + val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT; > + writel(val, &disp->disp_interface_ctrl); > + } > > /* >* The pixel clock divider is in 7.1 format (where the bottom bit > @@ -147,7 +154,8 @@ static int update_display_mode(struct dc_disp_reg *disp, > div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2; > debug("Display clock %lu, divid
[PATCH v6 01/18] video: tegra20: dc: diverge DC per-SOC
Diverge DC driver setup to better fit each of supported generations of Tegra SOC. Tested-by: Agneli # Toshiba AC100 T20 Tested-by: Robert Eckelmann # ASUS TF101 Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565 Tested-by: Ion Agorria # HTC One X Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114 Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/tegra114-u-boot.dtsi| 13 +++ arch/arm/dts/tegra114.dtsi | 4 +- arch/arm/dts/tegra30-u-boot.dtsi | 4 + arch/arm/dts/tegra30.dtsi| 2 +- arch/arm/include/asm/arch-tegra114/display.h | 28 + arch/arm/include/asm/arch-tegra114/pwm.h | 13 +++ drivers/video/tegra20/tegra-dc.c | 107 +-- 7 files changed, 133 insertions(+), 38 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra114/display.h create mode 100644 arch/arm/include/asm/arch-tegra114/pwm.h diff --git a/arch/arm/dts/tegra114-u-boot.dtsi b/arch/arm/dts/tegra114-u-boot.dtsi index 7c11972552..6a02714a25 100644 --- a/arch/arm/dts/tegra114-u-boot.dtsi +++ b/arch/arm/dts/tegra114-u-boot.dtsi @@ -1,3 +1,16 @@ #include #include "tegra-u-boot.dtsi" + +/ { + host1x@5000 { + bootph-all; + dc@5420 { + bootph-all; + }; + + dc@5424 { + bootph-all; + }; + }; +}; diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index 68ee7f3165..250d692f6b 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -42,7 +42,7 @@ }; dc@5420 { - compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra114-dc"; reg = <0x5420 0x0004>; interrupts = ; clocks = <&tegra_car TEGRA114_CLK_DISP1>, @@ -61,7 +61,7 @@ }; dc@5424 { - compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra114-dc"; reg = <0x5424 0x0004>; interrupts = ; clocks = <&tegra_car TEGRA114_CLK_DISP2>, diff --git a/arch/arm/dts/tegra30-u-boot.dtsi b/arch/arm/dts/tegra30-u-boot.dtsi index 3038227dbe..6a02714a25 100644 --- a/arch/arm/dts/tegra30-u-boot.dtsi +++ b/arch/arm/dts/tegra30-u-boot.dtsi @@ -8,5 +8,9 @@ dc@5420 { bootph-all; }; + + dc@5424 { + bootph-all; + }; }; }; diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index f198bc0edb..1177e2ab1f 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -158,7 +158,7 @@ }; dc@5420 { - compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra30-dc"; reg = <0x5420 0x0004>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_DISP1>, diff --git a/arch/arm/include/asm/arch-tegra114/display.h b/arch/arm/include/asm/arch-tegra114/display.h new file mode 100644 index 00..9411525799 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/display.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * NVIDIA Corporation + */ + +#ifndef __ASM_ARCH_TEGRA_DISPLAY_H +#define __ASM_ARCH_TEGRA_DISPLAY_H + +#include + +/* This holds information about a window which can be displayed */ +struct disp_ctl_win { + enum win_color_depth_id fmt;/* Color depth/format */ + unsigned intbpp;/* Bits per pixel */ + phys_addr_t phys_addr; /* Physical address in memory */ + unsigned intx; /* Horizontal address offset (bytes) */ + unsigned inty; /* Veritical address offset (bytes) */ + unsigned intw; /* Width of source window */ + unsigned inth; /* Height of source window */ + unsigned intstride; /* Number of bytes per line */ + unsigned intout_x; /* Left edge of output window (col) */ + unsigned intout_y; /* Top edge of output window (row) */ + unsigned intout_w; /* Width of output window in pixels */ + unsigned intout_h; /* Height of output window in pixels */ +}; + +#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ diff --git a/arch/arm/include/asm/arch-tegra114/pwm.h b/arch/arm/include/asm/arch-tegra114/pwm.h new file mode 100644 index 00..af39151803 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/pwm.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + *