Re: [PATCH v8 1/5] spi: rockchip_sfc: add support for Rockchip SFC
On Mon, Aug 16, 2021 at 09:00:59PM +0800, Jon Lin wrote:
>
> On 2021/8/14 0:48, Chris Morgan wrote:
> > On Fri, Aug 13, 2021 at 09:53:03AM +0800, Jon Lin wrote:
> > > Here is the point, Can you take a try.
> > >
> > > diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
> > > index 8173724ecd..33c5344c70 100644
> > > --- a/drivers/spi/rockchip_sfc.c
> > > +++ b/drivers/spi/rockchip_sfc.c
> > > @@ -591,7 +591,7 @@ static int rockchip_sfc_adjust_op_size(struct
> > > spi_slave
> > > *mem, struct spi_mem_op
> > >
> > > static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
> > > {
> > > - struct rockchip_sfc *sfc = dev_get_priv(bus);
> > > + struct rockchip_sfc *sfc = dev_get_plat(bus);
> > > int ret;
> > >
> > > if (speed > sfc->max_freq)
> > > @@ -609,7 +609,7 @@ static int rockchip_sfc_set_speed(struct udevice *bus,
> > > uint speed)
> > > }
> > > sfc->speed = speed;
> > > #else
> > > - dev_dbg(sfc->dev, "sfc failed, CLK not support\n", __func__);
> > > + dev_dbg(sfc->dev, "sfc failed, CLK not support\n");
> > > #endif
> > > return 0;
> > > }
> > >
> > This "works", but now I'm getting a MASSIVE performance regression.
> >
> > => sf test 0xc0 0x40
> > SPI flash test:
> > 0 erase: 91154 ticks, 44 KiB/s 0.352 Mbps
> > 1 check: 94878 ticks, 43 KiB/s 0.344 Mbps
> > 2 write: 199305 ticks, 20 KiB/s 0.160 Mbps
> > 3 read: 94808 ticks, 43 KiB/s 0.344 Mbps
> > Test passed
> >
> > Reads used to be on the order of 5MB/s and writes, while slower, were
> > still considerably faster.
>
> I try it with sf test too:
>
> => sf probe 4:0 5000
> SF: Detected w25q256fw with page size 256 Bytes, erase size 4 KiB, total 32
> MiB
> => sf test 0xc0 0x40
> SPI flash test:
> 0 erase: 32778 ticks, 124 KiB/s 0.992 Mbps
> 1 check: 688 ticks, 5953 KiB/s 47.624 Mbps
> 2 write: 7760 ticks, 527 KiB/s 4.216 Mbps
> 3 read: 672 ticks, 6095 KiB/s 48.760 Mbps
> Test passed
> 0 erase: 32778 ticks, 124 KiB/s 0.992 Mbps
> 1 check: 688 ticks, 5953 KiB/s 47.624 Mbps
> 2 write: 7760 ticks, 527 KiB/s 4.216 Mbps
> 3 read: 672 ticks, 6095 KiB/s 48.760 Mbps
>
>
> => sf probe 4:0 1
> SF: Detected w25q256fw with page size 256 Bytes, erase size 4 KiB, total 32
> MiB
> => sf test 0xc0 0x40
> SPI flash test:
> 0 erase: 32730 ticks, 125 KiB/s 1.000 Mbps
> 1 check: 355 ticks, 11538 KiB/s 92.304 Mbps
> 2 write: 7414 ticks, 552 KiB/s 4.416 Mbps
> 3 read: 340 ticks, 12047 KiB/s 96.376 Mbps
> Test passed
> 0 erase: 32730 ticks, 125 KiB/s 1.000 Mbps
> 1 check: 355 ticks, 11538 KiB/s 92.304 Mbps
> 2 write: 7414 ticks, 552 KiB/s 4.416 Mbps
> 3 read: 340 ticks, 12047 KiB/s 96.376 Mbps
> =>
>
> with main feature:
>
> - dma enable
>
> - tx/rx single line
I blame myself as I think I was using the wrong patch series for
testing. Let's look at the possibility of rebasing if there are any
more changes to be made as it looks like some of this has already been
added to mainline. I went through my divergence from mainline a bit at
a time and found the following.
With just the patch applied from here (necessary to make the board
boot):
https://patchwork.ozlabs.org/project/uboot/cover/20210805164848.21001-1-macroalph...@gmail.com/
=> sf test 0xc0 0x40
SPI flash test:
0 erase: 86593 ticks, 47 KiB/s 0.376 Mbps
1 check: 407 ticks, 10063 KiB/s 80.504 Mbps
2 write: 4800 ticks, 853 KiB/s 6.824 Mbps
3 read: 337 ticks, 12154 KiB/s 97.232 Mbps
Test passed
Modified the devicetree to match exactly what is proposed for the
upstream Linux implementation (so there is no divergence at all
in the devicetree, at least for the sfc node and flash node).
=> sf test 0xc0 0x40
SPI flash test:
0 erase: 88896 ticks, 46 KiB/s 0.368 Mbps
1 check: 408 ticks, 10039 KiB/s 80.312 Mbps
2 write: 4769 ticks, 858 KiB/s 6.864 Mbps
3 read: 337 ticks, 12154 KiB/s 97.232 Mbps
Test passed
Added the "sfc-no-dma" parameter so that we can boot entirely off of
the SFC.
=> sf test 0xc0 0x40
SPI flash test:
0 erase: 89125 ticks, 45 KiB/s 0.360 Mbps
1 check: 407 ticks, 10063 KiB/s 80.504 Mbps
2 write: 4761 ticks, 860 KiB/s 6.880 Mbps
3 read: 337 ticks, 12154 KiB/s 97.232 Mbps
Test passed
So I assume I was doing something wrong in my testing. Again, since a
good portion of this is now upstream, can we rebase if there are any
more changes though? Thank you again for all your hard work on this.
>
> If you need any more test, You can check with me further. I think you should
> first confirm the IO actual speed and the actual bottleneck.
>
> > > On 2021/8/13 3:13, Chris Morgan wrote:
> > > > On Thu, Aug 12, 2021 at 09:15:14PM +0800, Jon Lin wrote:
> > > > > From: Chris Morgan
> > > > >
> > > > > This patch adds support for the Rockchip serial flash controller
> > > > > found on the PX30 SoC. It should work for versions 3-5 of the SFC
> > > > > IP, however I am only able to test it on v3.
> > > > >
> > > > > This is adapted from the WIP
Re: [PATCH v8 1/5] spi: rockchip_sfc: add support for Rockchip SFC
On 2021/8/16 23:22, Chris Morgan wrote:
On Mon, Aug 16, 2021 at 09:00:59PM +0800, Jon Lin wrote:
On 2021/8/14 0:48, Chris Morgan wrote:
On Fri, Aug 13, 2021 at 09:53:03AM +0800, Jon Lin wrote:
Here is the point, Can you take a try.
diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
index 8173724ecd..33c5344c70 100644
--- a/drivers/spi/rockchip_sfc.c
+++ b/drivers/spi/rockchip_sfc.c
@@ -591,7 +591,7 @@ static int rockchip_sfc_adjust_op_size(struct spi_slave
*mem, struct spi_mem_op
static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
{
- struct rockchip_sfc *sfc = dev_get_priv(bus);
+ struct rockchip_sfc *sfc = dev_get_plat(bus);
int ret;
if (speed > sfc->max_freq)
@@ -609,7 +609,7 @@ static int rockchip_sfc_set_speed(struct udevice *bus,
uint speed)
}
sfc->speed = speed;
#else
- dev_dbg(sfc->dev, "sfc failed, CLK not support\n", __func__);
+ dev_dbg(sfc->dev, "sfc failed, CLK not support\n");
#endif
return 0;
}
This "works", but now I'm getting a MASSIVE performance regression.
=> sf test 0xc0 0x40
SPI flash test:
0 erase: 91154 ticks, 44 KiB/s 0.352 Mbps
1 check: 94878 ticks, 43 KiB/s 0.344 Mbps
2 write: 199305 ticks, 20 KiB/s 0.160 Mbps
3 read: 94808 ticks, 43 KiB/s 0.344 Mbps
Test passed
Reads used to be on the order of 5MB/s and writes, while slower, were
still considerably faster.
I try it with sf test too:
=> sf probe 4:0 5000
SF: Detected w25q256fw with page size 256 Bytes, erase size 4 KiB, total 32
MiB
=> sf test 0xc0 0x40
SPI flash test:
0 erase: 32778 ticks, 124 KiB/s 0.992 Mbps
1 check: 688 ticks, 5953 KiB/s 47.624 Mbps
2 write: 7760 ticks, 527 KiB/s 4.216 Mbps
3 read: 672 ticks, 6095 KiB/s 48.760 Mbps
Test passed
0 erase: 32778 ticks, 124 KiB/s 0.992 Mbps
1 check: 688 ticks, 5953 KiB/s 47.624 Mbps
2 write: 7760 ticks, 527 KiB/s 4.216 Mbps
3 read: 672 ticks, 6095 KiB/s 48.760 Mbps
=> sf probe 4:0 1
SF: Detected w25q256fw with page size 256 Bytes, erase size 4 KiB, total 32
MiB
=> sf test 0xc0 0x40
SPI flash test:
0 erase: 32730 ticks, 125 KiB/s 1.000 Mbps
1 check: 355 ticks, 11538 KiB/s 92.304 Mbps
2 write: 7414 ticks, 552 KiB/s 4.416 Mbps
3 read: 340 ticks, 12047 KiB/s 96.376 Mbps
Test passed
0 erase: 32730 ticks, 125 KiB/s 1.000 Mbps
1 check: 355 ticks, 11538 KiB/s 92.304 Mbps
2 write: 7414 ticks, 552 KiB/s 4.416 Mbps
3 read: 340 ticks, 12047 KiB/s 96.376 Mbps
=>
with main feature:
- dma enable
- tx/rx single line
I blame myself as I think I was using the wrong patch series for
testing. Let's look at the possibility of rebasing if there are any
more changes to be made as it looks like some of this has already been
added to mainline. I went through my divergence from mainline a bit at
a time and found the following.
With just the patch applied from here (necessary to make the board
boot):
https://patchwork.ozlabs.org/project/uboot/cover/20210805164848.21001-1-macroalph...@gmail.com/
=> sf test 0xc0 0x40
SPI flash test:
0 erase: 86593 ticks, 47 KiB/s 0.376 Mbps
1 check: 407 ticks, 10063 KiB/s 80.504 Mbps
2 write: 4800 ticks, 853 KiB/s 6.824 Mbps
3 read: 337 ticks, 12154 KiB/s 97.232 Mbps
Test passed
Modified the devicetree to match exactly what is proposed for the
upstream Linux implementation (so there is no divergence at all
in the devicetree, at least for the sfc node and flash node).
=> sf test 0xc0 0x40
SPI flash test:
0 erase: 88896 ticks, 46 KiB/s 0.368 Mbps
1 check: 408 ticks, 10039 KiB/s 80.312 Mbps
2 write: 4769 ticks, 858 KiB/s 6.864 Mbps
3 read: 337 ticks, 12154 KiB/s 97.232 Mbps
Test passed
Added the "sfc-no-dma" parameter so that we can boot entirely off of
the SFC.
=> sf test 0xc0 0x40
SPI flash test:
0 erase: 89125 ticks, 45 KiB/s 0.360 Mbps
1 check: 407 ticks, 10063 KiB/s 80.504 Mbps
2 write: 4761 ticks, 860 KiB/s 6.880 Mbps
3 read: 337 ticks, 12154 KiB/s 97.232 Mbps
Test passed
So I assume I was doing something wrong in my testing. Again, since a
good portion of this is now upstream, can we rebase if there are any
more changes though? Thank you again for all your hard work on this.
I've upstreamed the deference between [V8 RFC] with master branch.
https://patchwork.ozlabs.org/project/uboot/patch/20210817093621.1.Id0647655ab4060f95c9a49fe834465bbe39b8d31@changeid/
So Chris please check it again.
If you need any more test, You can check with me further. I think you should
first confirm the IO actual speed and the actual bottleneck.
On 2021/8/13 3:13, Chris Morgan wrote:
On Thu, Aug 12, 2021 at 09:15:14PM +0800, Jon Lin wrote:
From: Chris Morgan
This patch adds support for the Rockchip serial flash controller
found on the PX30 SoC. It should work for versions 3-5 of the SFC
IP, however I am only able to test it on v3.
This is adapted from the WIP SPI-MEM driver for the SFC on mainline
Linux. Note that the main difference between this and earlier versions
of
Re: [PATCH v8 1/5] spi: rockchip_sfc: add support for Rockchip SFC
On 2021/8/14 0:48, Chris Morgan wrote:
On Fri, Aug 13, 2021 at 09:53:03AM +0800, Jon Lin wrote:
Here is the point, Can you take a try.
diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
index 8173724ecd..33c5344c70 100644
--- a/drivers/spi/rockchip_sfc.c
+++ b/drivers/spi/rockchip_sfc.c
@@ -591,7 +591,7 @@ static int rockchip_sfc_adjust_op_size(struct spi_slave
*mem, struct spi_mem_op
static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
{
- struct rockchip_sfc *sfc = dev_get_priv(bus);
+ struct rockchip_sfc *sfc = dev_get_plat(bus);
int ret;
if (speed > sfc->max_freq)
@@ -609,7 +609,7 @@ static int rockchip_sfc_set_speed(struct udevice *bus,
uint speed)
}
sfc->speed = speed;
#else
- dev_dbg(sfc->dev, "sfc failed, CLK not support\n", __func__);
+ dev_dbg(sfc->dev, "sfc failed, CLK not support\n");
#endif
return 0;
}
This "works", but now I'm getting a MASSIVE performance regression.
=> sf test 0xc0 0x40
SPI flash test:
0 erase: 91154 ticks, 44 KiB/s 0.352 Mbps
1 check: 94878 ticks, 43 KiB/s 0.344 Mbps
2 write: 199305 ticks, 20 KiB/s 0.160 Mbps
3 read: 94808 ticks, 43 KiB/s 0.344 Mbps
Test passed
Reads used to be on the order of 5MB/s and writes, while slower, were
still considerably faster.
I try it with sf test too:
=> sf probe 4:0 5000
SF: Detected w25q256fw with page size 256 Bytes, erase size 4 KiB, total
32 MiB
=> sf test 0xc0 0x40
SPI flash test:
0 erase: 32778 ticks, 124 KiB/s 0.992 Mbps
1 check: 688 ticks, 5953 KiB/s 47.624 Mbps
2 write: 7760 ticks, 527 KiB/s 4.216 Mbps
3 read: 672 ticks, 6095 KiB/s 48.760 Mbps
Test passed
0 erase: 32778 ticks, 124 KiB/s 0.992 Mbps
1 check: 688 ticks, 5953 KiB/s 47.624 Mbps
2 write: 7760 ticks, 527 KiB/s 4.216 Mbps
3 read: 672 ticks, 6095 KiB/s 48.760 Mbps
=> sf probe 4:0 1
SF: Detected w25q256fw with page size 256 Bytes, erase size 4 KiB, total
32 MiB
=> sf test 0xc0 0x40
SPI flash test:
0 erase: 32730 ticks, 125 KiB/s 1.000 Mbps
1 check: 355 ticks, 11538 KiB/s 92.304 Mbps
2 write: 7414 ticks, 552 KiB/s 4.416 Mbps
3 read: 340 ticks, 12047 KiB/s 96.376 Mbps
Test passed
0 erase: 32730 ticks, 125 KiB/s 1.000 Mbps
1 check: 355 ticks, 11538 KiB/s 92.304 Mbps
2 write: 7414 ticks, 552 KiB/s 4.416 Mbps
3 read: 340 ticks, 12047 KiB/s 96.376 Mbps
=>
with main feature:
- dma enable
- tx/rx single line
If you need any more test, You can check with me further. I think you
should first confirm the IO actual speed and the actual bottleneck.
On 2021/8/13 3:13, Chris Morgan wrote:
On Thu, Aug 12, 2021 at 09:15:14PM +0800, Jon Lin wrote:
From: Chris Morgan
This patch adds support for the Rockchip serial flash controller
found on the PX30 SoC. It should work for versions 3-5 of the SFC
IP, however I am only able to test it on v3.
This is adapted from the WIP SPI-MEM driver for the SFC on mainline
Linux. Note that the main difference between this and earlier versions
of the driver is that this one does not support DMA. In testing
the performance difference (performing a dual mode read on a 128Mb
chip) is negligible. DMA, if used, must also be disabled in SPL
mode when using A-TF anyway.
Signed-off-by: Chris Morgan
Signed-off-by: Jon Lin
---
I'll need to debug it further, but unfortunately this is not working
for me. On my Odroid Go Advance I get a "Synchronous Abort" error when
I attempt to do an "sf probe". This same sequence (boot, then do sf
probe) has worked on all prior revisions without a crash.
U-Boot TPL board init
DDR3, 333MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
out
U-Boot SPL 2021.10-rc1+ (Aug 12 2021 - 14:03:30 -0500)
Trying to boot from MMC1
NOTICE: BL31: v2.5(release):v2.5-284-g87311b4c1
NOTICE: BL31: Built : 10:43:59, Aug 5 2021
U-Boot 2021.10-rc1+ (Aug 12 2021 - 14:03:30 -0500)
Model: ODROID-GO Advance
DRAM: 1022 MiB
PMIC: RK8170 (on=0x80, off=0x04)
MMC: dwmmc@ff37: 0
Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
In:serial@ff16
Out: serial@ff16
Err: serial@ff16
Model: ODROID-GO Advance
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
MMC Device 1 not found
no mmc device at slot 1
starting USB...
Bus usb@ff30: probe failed, error -2
No working controllers found
USB is stopped. Please issue 'usb start' first.
=> sf probe
"Synchronous Abort" handler, esr 0x9610
elr: 0022d730 lr : 0022d72c (reloc)
elr: 3ff85730 lr : 3ff8572c
x0 : x1 : 066ff300
x2 : 3ff85714 x3 :
x4 : 3ffccd1d x5 : 006e
x6 : 3ffba6d8 x7 : 0044
x8 : 000a x9 : 0008
x10: 0034 x11: 0003
x12: x13: ffd8
x14: 3df485d0 x15: 0002
x16: 3ff8ebe8 x17: 0001
Re: [PATCH v8 1/5] spi: rockchip_sfc: add support for Rockchip SFC
On Fri, Aug 13, 2021 at 09:53:03AM +0800, Jon Lin wrote:
>
> Here is the point, Can you take a try.
>
> diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
> index 8173724ecd..33c5344c70 100644
> --- a/drivers/spi/rockchip_sfc.c
> +++ b/drivers/spi/rockchip_sfc.c
> @@ -591,7 +591,7 @@ static int rockchip_sfc_adjust_op_size(struct spi_slave
> *mem, struct spi_mem_op
>
> static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
> {
> - struct rockchip_sfc *sfc = dev_get_priv(bus);
> + struct rockchip_sfc *sfc = dev_get_plat(bus);
> int ret;
>
> if (speed > sfc->max_freq)
> @@ -609,7 +609,7 @@ static int rockchip_sfc_set_speed(struct udevice *bus,
> uint speed)
> }
> sfc->speed = speed;
> #else
> - dev_dbg(sfc->dev, "sfc failed, CLK not support\n", __func__);
> + dev_dbg(sfc->dev, "sfc failed, CLK not support\n");
> #endif
> return 0;
> }
>
This "works", but now I'm getting a MASSIVE performance regression.
=> sf test 0xc0 0x40
SPI flash test:
0 erase: 91154 ticks, 44 KiB/s 0.352 Mbps
1 check: 94878 ticks, 43 KiB/s 0.344 Mbps
2 write: 199305 ticks, 20 KiB/s 0.160 Mbps
3 read: 94808 ticks, 43 KiB/s 0.344 Mbps
Test passed
Reads used to be on the order of 5MB/s and writes, while slower, were
still considerably faster.
>
> On 2021/8/13 3:13, Chris Morgan wrote:
> > On Thu, Aug 12, 2021 at 09:15:14PM +0800, Jon Lin wrote:
> > > From: Chris Morgan
> > >
> > > This patch adds support for the Rockchip serial flash controller
> > > found on the PX30 SoC. It should work for versions 3-5 of the SFC
> > > IP, however I am only able to test it on v3.
> > >
> > > This is adapted from the WIP SPI-MEM driver for the SFC on mainline
> > > Linux. Note that the main difference between this and earlier versions
> > > of the driver is that this one does not support DMA. In testing
> > > the performance difference (performing a dual mode read on a 128Mb
> > > chip) is negligible. DMA, if used, must also be disabled in SPL
> > > mode when using A-TF anyway.
> > >
> > > Signed-off-by: Chris Morgan
> > > Signed-off-by: Jon Lin
> > > ---
> > >
> > I'll need to debug it further, but unfortunately this is not working
> > for me. On my Odroid Go Advance I get a "Synchronous Abort" error when
> > I attempt to do an "sf probe". This same sequence (boot, then do sf
> > probe) has worked on all prior revisions without a crash.
> >
> > U-Boot TPL board init
> > DDR3, 333MHz
> > BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
> > out
> >
> > U-Boot SPL 2021.10-rc1+ (Aug 12 2021 - 14:03:30 -0500)
> > Trying to boot from MMC1
> > NOTICE: BL31: v2.5(release):v2.5-284-g87311b4c1
> > NOTICE: BL31: Built : 10:43:59, Aug 5 2021
> >
> >
> > U-Boot 2021.10-rc1+ (Aug 12 2021 - 14:03:30 -0500)
> >
> > Model: ODROID-GO Advance
> > DRAM: 1022 MiB
> > PMIC: RK8170 (on=0x80, off=0x04)
> > MMC: dwmmc@ff37: 0
> > Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
> > In:serial@ff16
> > Out: serial@ff16
> > Err: serial@ff16
> > Model: ODROID-GO Advance
> > Hit any key to stop autoboot: 0
> > switch to partitions #0, OK
> > mmc0 is current device
> > Scanning mmc 0:1...
> > MMC Device 1 not found
> > no mmc device at slot 1
> > starting USB...
> > Bus usb@ff30: probe failed, error -2
> > No working controllers found
> > USB is stopped. Please issue 'usb start' first.
> > => sf probe
> > "Synchronous Abort" handler, esr 0x9610
> > elr: 0022d730 lr : 0022d72c (reloc)
> > elr: 3ff85730 lr : 3ff8572c
> > x0 : x1 : 066ff300
> > x2 : 3ff85714 x3 :
> > x4 : 3ffccd1d x5 : 006e
> > x6 : 3ffba6d8 x7 : 0044
> > x8 : 000a x9 : 0008
> > x10: 0034 x11: 0003
> > x12: x13: ffd8
> > x14: 3df485d0 x15: 0002
> > x16: 3ff8ebe8 x17: 0001
> > x18: 3df53dd0 x19: 066ff300
> > x20: x21: 066ff300
> > x22: 3ffbdef8 x23: 1000
> > x24: 3df6f530 x25: 3df92e90
> > x26: 3ffeecc0 x27:
> > x28: 0003 x29: 3df481c0
> >
> > Code: f90013f5 2a0103f5 94003427 aa0003f4 (294c0013)
> > Resetting CPU ...
> >
> > resetting ...
> >
> >
> > > Changes in v8:
> > > - Move speed operation to set_speed logic
> > > - Use read_poll
> > > - Change debug to dev_dbg
> > > - Simply exec_op dma logic
> > >
> > > Changes in v7:
> > > - Make sfc-use-dma configurable
> > >
> > > Changes in v6:
> > > - Fix dma transfer logic
> > > - Fix the error of the way to wait for dma transfer finished status
> > >
> > > Changes in v5:
> > > - Support dma transfer
> > > - Add CONFIG_IS_ENABLED(CLK) limitation
> > > - Support spinand devices
> > > - Support SFC ver4 ver5
> > > -
Re: [PATCH v8 1/5] spi: rockchip_sfc: add support for Rockchip SFC
Here is the point, Can you take a try.
diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
index 8173724ecd..33c5344c70 100644
--- a/drivers/spi/rockchip_sfc.c
+++ b/drivers/spi/rockchip_sfc.c
@@ -591,7 +591,7 @@ static int rockchip_sfc_adjust_op_size(struct
spi_slave *mem, struct spi_mem_op
static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
{
- struct rockchip_sfc *sfc = dev_get_priv(bus);
+ struct rockchip_sfc *sfc = dev_get_plat(bus);
int ret;
if (speed > sfc->max_freq)
@@ -609,7 +609,7 @@ static int rockchip_sfc_set_speed(struct udevice
*bus, uint speed)
}
sfc->speed = speed;
#else
- dev_dbg(sfc->dev, "sfc failed, CLK not support\n", __func__);
+ dev_dbg(sfc->dev, "sfc failed, CLK not support\n");
#endif
return 0;
}
On 2021/8/13 3:13, Chris Morgan wrote:
On Thu, Aug 12, 2021 at 09:15:14PM +0800, Jon Lin wrote:
From: Chris Morgan
This patch adds support for the Rockchip serial flash controller
found on the PX30 SoC. It should work for versions 3-5 of the SFC
IP, however I am only able to test it on v3.
This is adapted from the WIP SPI-MEM driver for the SFC on mainline
Linux. Note that the main difference between this and earlier versions
of the driver is that this one does not support DMA. In testing
the performance difference (performing a dual mode read on a 128Mb
chip) is negligible. DMA, if used, must also be disabled in SPL
mode when using A-TF anyway.
Signed-off-by: Chris Morgan
Signed-off-by: Jon Lin
---
I'll need to debug it further, but unfortunately this is not working
for me. On my Odroid Go Advance I get a "Synchronous Abort" error when
I attempt to do an "sf probe". This same sequence (boot, then do sf
probe) has worked on all prior revisions without a crash.
U-Boot TPL board init
DDR3, 333MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
out
U-Boot SPL 2021.10-rc1+ (Aug 12 2021 - 14:03:30 -0500)
Trying to boot from MMC1
NOTICE: BL31: v2.5(release):v2.5-284-g87311b4c1
NOTICE: BL31: Built : 10:43:59, Aug 5 2021
U-Boot 2021.10-rc1+ (Aug 12 2021 - 14:03:30 -0500)
Model: ODROID-GO Advance
DRAM: 1022 MiB
PMIC: RK8170 (on=0x80, off=0x04)
MMC: dwmmc@ff37: 0
Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
In:serial@ff16
Out: serial@ff16
Err: serial@ff16
Model: ODROID-GO Advance
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
MMC Device 1 not found
no mmc device at slot 1
starting USB...
Bus usb@ff30: probe failed, error -2
No working controllers found
USB is stopped. Please issue 'usb start' first.
=> sf probe
"Synchronous Abort" handler, esr 0x9610
elr: 0022d730 lr : 0022d72c (reloc)
elr: 3ff85730 lr : 3ff8572c
x0 : x1 : 066ff300
x2 : 3ff85714 x3 :
x4 : 3ffccd1d x5 : 006e
x6 : 3ffba6d8 x7 : 0044
x8 : 000a x9 : 0008
x10: 0034 x11: 0003
x12: x13: ffd8
x14: 3df485d0 x15: 0002
x16: 3ff8ebe8 x17: 0001
x18: 3df53dd0 x19: 066ff300
x20: x21: 066ff300
x22: 3ffbdef8 x23: 1000
x24: 3df6f530 x25: 3df92e90
x26: 3ffeecc0 x27:
x28: 0003 x29: 3df481c0
Code: f90013f5 2a0103f5 94003427 aa0003f4 (294c0013)
Resetting CPU ...
resetting ...
Changes in v8:
- Move speed operation to set_speed logic
- Use read_poll
- Change debug to dev_dbg
- Simply exec_op dma logic
Changes in v7:
- Make sfc-use-dma configurable
Changes in v6:
- Fix dma transfer logic
- Fix the error of the way to wait for dma transfer finished status
Changes in v5:
- Support dma transfer
- Add CONFIG_IS_ENABLED(CLK) limitation
- Support spinand devices
- Support SFC ver4 ver5
- Using "rockchip, sfc" as compatible id
- Get clock from the index to compatible with those case which's
clock-names is not parsed
Changes in v4:
- None
Changes in v3:
- Added "rockchip_sfc_adjust_op_work()" function from proposed Linux
driver to fix potential issue on hardware. Note I never noticed
this issue while testing, so I cannot test if it fixed any specific
issue for me.
- Updated of-compatible string back to "rockchip,sfc" to match what
is currently proposed for upstream driver. The hardware itself
has multiple versions but a register is present in the hardware that
is read by the driver to set version specific functionality.
- Updated px30.dtsi and rk3266-odroid-go2.dts device-trees so that
sfc nodes match what is in upstream.
Changes in v2:
- Resending due to glitch with patch file truncating final two lines
on patch 1/5 and incorrect patch version number on patch 5/5.
Changes in v1:
- Reworked code to utilize spi-mem
Re: [PATCH v8 1/5] spi: rockchip_sfc: add support for Rockchip SFC
On Thu, Aug 12, 2021 at 09:15:14PM +0800, Jon Lin wrote: > From: Chris Morgan > > This patch adds support for the Rockchip serial flash controller > found on the PX30 SoC. It should work for versions 3-5 of the SFC > IP, however I am only able to test it on v3. > > This is adapted from the WIP SPI-MEM driver for the SFC on mainline > Linux. Note that the main difference between this and earlier versions > of the driver is that this one does not support DMA. In testing > the performance difference (performing a dual mode read on a 128Mb > chip) is negligible. DMA, if used, must also be disabled in SPL > mode when using A-TF anyway. > > Signed-off-by: Chris Morgan > Signed-off-by: Jon Lin > --- > I'll need to debug it further, but unfortunately this is not working for me. On my Odroid Go Advance I get a "Synchronous Abort" error when I attempt to do an "sf probe". This same sequence (boot, then do sf probe) has worked on all prior revisions without a crash. U-Boot TPL board init DDR3, 333MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB out U-Boot SPL 2021.10-rc1+ (Aug 12 2021 - 14:03:30 -0500) Trying to boot from MMC1 NOTICE: BL31: v2.5(release):v2.5-284-g87311b4c1 NOTICE: BL31: Built : 10:43:59, Aug 5 2021 U-Boot 2021.10-rc1+ (Aug 12 2021 - 14:03:30 -0500) Model: ODROID-GO Advance DRAM: 1022 MiB PMIC: RK8170 (on=0x80, off=0x04) MMC: dwmmc@ff37: 0 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1... In:serial@ff16 Out: serial@ff16 Err: serial@ff16 Model: ODROID-GO Advance Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0 is current device Scanning mmc 0:1... MMC Device 1 not found no mmc device at slot 1 starting USB... Bus usb@ff30: probe failed, error -2 No working controllers found USB is stopped. Please issue 'usb start' first. => sf probe "Synchronous Abort" handler, esr 0x9610 elr: 0022d730 lr : 0022d72c (reloc) elr: 3ff85730 lr : 3ff8572c x0 : x1 : 066ff300 x2 : 3ff85714 x3 : x4 : 3ffccd1d x5 : 006e x6 : 3ffba6d8 x7 : 0044 x8 : 000a x9 : 0008 x10: 0034 x11: 0003 x12: x13: ffd8 x14: 3df485d0 x15: 0002 x16: 3ff8ebe8 x17: 0001 x18: 3df53dd0 x19: 066ff300 x20: x21: 066ff300 x22: 3ffbdef8 x23: 1000 x24: 3df6f530 x25: 3df92e90 x26: 3ffeecc0 x27: x28: 0003 x29: 3df481c0 Code: f90013f5 2a0103f5 94003427 aa0003f4 (294c0013) Resetting CPU ... resetting ... > Changes in v8: > - Move speed operation to set_speed logic > - Use read_poll > - Change debug to dev_dbg > - Simply exec_op dma logic > > Changes in v7: > - Make sfc-use-dma configurable > > Changes in v6: > - Fix dma transfer logic > - Fix the error of the way to wait for dma transfer finished status > > Changes in v5: > - Support dma transfer > - Add CONFIG_IS_ENABLED(CLK) limitation > - Support spinand devices > - Support SFC ver4 ver5 > - Using "rockchip, sfc" as compatible id > - Get clock from the index to compatible with those case which's > clock-names is not parsed > > Changes in v4: > - None > > Changes in v3: > - Added "rockchip_sfc_adjust_op_work()" function from proposed Linux > driver to fix potential issue on hardware. Note I never noticed > this issue while testing, so I cannot test if it fixed any specific > issue for me. > - Updated of-compatible string back to "rockchip,sfc" to match what > is currently proposed for upstream driver. The hardware itself > has multiple versions but a register is present in the hardware that > is read by the driver to set version specific functionality. > - Updated px30.dtsi and rk3266-odroid-go2.dts device-trees so that > sfc nodes match what is in upstream. > > Changes in v2: > - Resending due to glitch with patch file truncating final two lines > on patch 1/5 and incorrect patch version number on patch 5/5. > > Changes in v1: > - Reworked code to utilize spi-mem framework, and based it closely > off of work in progress code for mainline Linux. > - Removed DMA, as it didn't offer much performance benefit for > booting (in my test cases), added complexity to the code, and > interfered with A-TF. > - Updated the names of the bindings to match the work in progress > Linux code. > - Moved alias to u-boot specific device-tree for Odroid Go Advance. > Alias is updated with the spi0 node pointing to the SFC to > help the sf command as well as facilitate booting from the SFC. > - Note 2 below no longer applies, as rebasing this off of upstream > code should allow the device to work for NAND, and by utilizing > the spi-mem framework it no longer has to extract the parameters > > drivers/spi/Kconfig| 8 + >
[RFC PATCH v8 1/5] spi: rockchip_sfc: add support for Rockchip SFC
From: Chris Morgan This patch adds support for the Rockchip serial flash controller found on the PX30 SoC. It should work for versions 3-5 of the SFC IP, however I am only able to test it on v3. This is adapted from the WIP SPI-MEM driver for the SFC on mainline Linux. Note that the main difference between this and earlier versions of the driver is that this one does not support DMA. In testing the performance difference (performing a dual mode read on a 128Mb chip) is negligible. DMA, if used, must also be disabled in SPL mode when using A-TF anyway. Signed-off-by: Chris Morgan Signed-off-by: Jon Lin --- Changes in v8: - Move speed operation to set_speed logic - Use read_poll - Change debug to dev_dbg - Simply exec_op dma logic Changes in v7: - Make sfc-use-dma configurable Changes in v6: - Fix dma transfer logic - Fix the error of the way to wait for dma transfer finished status Changes in v5: - Support dma transfer - Add CONFIG_IS_ENABLED(CLK) limitation - Support spinand devices - Support SFC ver4 ver5 - Using "rockchip, sfc" as compatible id - Get clock from the index to compatible with those case which's clock-names is not parsed Changes in v4: - None Changes in v3: - Added "rockchip_sfc_adjust_op_work()" function from proposed Linux driver to fix potential issue on hardware. Note I never noticed this issue while testing, so I cannot test if it fixed any specific issue for me. - Updated of-compatible string back to "rockchip,sfc" to match what is currently proposed for upstream driver. The hardware itself has multiple versions but a register is present in the hardware that is read by the driver to set version specific functionality. - Updated px30.dtsi and rk3266-odroid-go2.dts device-trees so that sfc nodes match what is in upstream. Changes in v2: - Resending due to glitch with patch file truncating final two lines on patch 1/5 and incorrect patch version number on patch 5/5. Changes in v1: - Reworked code to utilize spi-mem framework, and based it closely off of work in progress code for mainline Linux. - Removed DMA, as it didn't offer much performance benefit for booting (in my test cases), added complexity to the code, and interfered with A-TF. - Updated the names of the bindings to match the work in progress Linux code. - Moved alias to u-boot specific device-tree for Odroid Go Advance. Alias is updated with the spi0 node pointing to the SFC to help the sf command as well as facilitate booting from the SFC. - Note 2 below no longer applies, as rebasing this off of upstream code should allow the device to work for NAND, and by utilizing the spi-mem framework it no longer has to extract the parameters drivers/spi/Kconfig| 8 + drivers/spi/Makefile | 1 + drivers/spi/rockchip_sfc.c | 646 + 3 files changed, 655 insertions(+) create mode 100644 drivers/spi/rockchip_sfc.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 5c2a60a214..e12699bec7 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -319,6 +319,14 @@ config RENESAS_RPC_SPI on Renesas RCar Gen3 SoCs. This uses driver model and requires a device tree binding to operate. +config ROCKCHIP_SFC + bool "Rockchip SFC Driver" + help + Enable the Rockchip SFC Driver for SPI NOR flash. This device is + a limited purpose SPI controller for driving NOR flash on certain + Rockchip SoCs. This uses driver model and requires a device tree + binding to operate. + config ROCKCHIP_SPI bool "Rockchip SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 216e72c60f..d2f24bccef 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o obj-$(CONFIG_SPI_QUP) += spi-qup.o obj-$(CONFIG_SPI_MXIC) += spi-mxic.o obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o +obj-$(CONFIG_ROCKCHIP_SFC) += rockchip_sfc.o obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c new file mode 100644 index 00..8173724ecd --- /dev/null +++ b/drivers/spi/rockchip_sfc.c @@ -0,0 +1,646 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Rockchip Serial Flash Controller Driver + * + * Copyright (c) 2017-2021, Rockchip Inc. + * Author: Shawn Lin + *Chris Morgan + *Jon Lin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* System control */ +#define SFC_CTRL 0x0 +#define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) +#define SFC_CTRL_CMD_BITS_SHIFT 8 +#define SFC_CTRL_ADDR_BITS_SHIFT 10 +#define SFC_CTRL_DATA_BITS_SHIFT 12 + +/* Interrupt mask */ +#define SFC_IMR0x4 +#define SFC_IMR_RX_FULL
[PATCH v8 1/5] spi: rockchip_sfc: add support for Rockchip SFC
From: Chris Morgan This patch adds support for the Rockchip serial flash controller found on the PX30 SoC. It should work for versions 3-5 of the SFC IP, however I am only able to test it on v3. This is adapted from the WIP SPI-MEM driver for the SFC on mainline Linux. Note that the main difference between this and earlier versions of the driver is that this one does not support DMA. In testing the performance difference (performing a dual mode read on a 128Mb chip) is negligible. DMA, if used, must also be disabled in SPL mode when using A-TF anyway. Signed-off-by: Chris Morgan Signed-off-by: Jon Lin --- Changes in v8: - Move speed operation to set_speed logic - Use read_poll - Change debug to dev_dbg - Simply exec_op dma logic Changes in v7: - Make sfc-use-dma configurable Changes in v6: - Fix dma transfer logic - Fix the error of the way to wait for dma transfer finished status Changes in v5: - Support dma transfer - Add CONFIG_IS_ENABLED(CLK) limitation - Support spinand devices - Support SFC ver4 ver5 - Using "rockchip, sfc" as compatible id - Get clock from the index to compatible with those case which's clock-names is not parsed Changes in v4: - None Changes in v3: - Added "rockchip_sfc_adjust_op_work()" function from proposed Linux driver to fix potential issue on hardware. Note I never noticed this issue while testing, so I cannot test if it fixed any specific issue for me. - Updated of-compatible string back to "rockchip,sfc" to match what is currently proposed for upstream driver. The hardware itself has multiple versions but a register is present in the hardware that is read by the driver to set version specific functionality. - Updated px30.dtsi and rk3266-odroid-go2.dts device-trees so that sfc nodes match what is in upstream. Changes in v2: - Resending due to glitch with patch file truncating final two lines on patch 1/5 and incorrect patch version number on patch 5/5. Changes in v1: - Reworked code to utilize spi-mem framework, and based it closely off of work in progress code for mainline Linux. - Removed DMA, as it didn't offer much performance benefit for booting (in my test cases), added complexity to the code, and interfered with A-TF. - Updated the names of the bindings to match the work in progress Linux code. - Moved alias to u-boot specific device-tree for Odroid Go Advance. Alias is updated with the spi0 node pointing to the SFC to help the sf command as well as facilitate booting from the SFC. - Note 2 below no longer applies, as rebasing this off of upstream code should allow the device to work for NAND, and by utilizing the spi-mem framework it no longer has to extract the parameters drivers/spi/Kconfig| 8 + drivers/spi/Makefile | 1 + drivers/spi/rockchip_sfc.c | 646 + 3 files changed, 655 insertions(+) create mode 100644 drivers/spi/rockchip_sfc.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 5c2a60a214..e12699bec7 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -319,6 +319,14 @@ config RENESAS_RPC_SPI on Renesas RCar Gen3 SoCs. This uses driver model and requires a device tree binding to operate. +config ROCKCHIP_SFC + bool "Rockchip SFC Driver" + help + Enable the Rockchip SFC Driver for SPI NOR flash. This device is + a limited purpose SPI controller for driving NOR flash on certain + Rockchip SoCs. This uses driver model and requires a device tree + binding to operate. + config ROCKCHIP_SPI bool "Rockchip SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 216e72c60f..d2f24bccef 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o obj-$(CONFIG_SPI_QUP) += spi-qup.o obj-$(CONFIG_SPI_MXIC) += spi-mxic.o obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o +obj-$(CONFIG_ROCKCHIP_SFC) += rockchip_sfc.o obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c new file mode 100644 index 00..8173724ecd --- /dev/null +++ b/drivers/spi/rockchip_sfc.c @@ -0,0 +1,646 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Rockchip Serial Flash Controller Driver + * + * Copyright (c) 2017-2021, Rockchip Inc. + * Author: Shawn Lin + *Chris Morgan + *Jon Lin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* System control */ +#define SFC_CTRL 0x0 +#define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) +#define SFC_CTRL_CMD_BITS_SHIFT 8 +#define SFC_CTRL_ADDR_BITS_SHIFT 10 +#define SFC_CTRL_DATA_BITS_SHIFT 12 + +/* Interrupt mask */ +#define SFC_IMR0x4 +#define SFC_IMR_RX_FULL
