[PATCH v9 14/21] riscv: Clean up IPI initialization code
The previous IPI code initialized the device whenever the first call was
made to a riscv_*_ipi function. This made it difficult to determine when
the IPI device was initialized. This patch introduces a new function
riscv_init_ipi. It is called once during arch_cpu_init_dm. Before this
point, no riscv_*_ipi functions should be called.
Signed-off-by: Sean Anderson
Reviewed-by: Rick Chen
---
Changes in v9:
- Fix type of ret variable in riscv_ipi_init
Changes in v7:
- Split IPI clearing off into its own patch
Changes in v6:
- Fix some formatting
- Clear IPIs before enabling interrupts instead of using a ipi_ready flag
- Only print messages on error in smp code
Changes in v5:
- New
arch/riscv/cpu/cpu.c | 6
arch/riscv/include/asm/smp.h | 43 +++
arch/riscv/lib/andes_plic.c | 34 -
arch/riscv/lib/sbi_ipi.c | 5
arch/riscv/lib/sifive_clint.c | 33 +++--
arch/riscv/lib/smp.c | 56 ---
6 files changed, 90 insertions(+), 87 deletions(-)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index e457f6acbf..f851374255 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -96,6 +96,12 @@ int arch_cpu_init_dm(void)
csr_write(CSR_SATP, 0);
}
+#ifdef CONFIG_SMP
+ ret = riscv_init_ipi();
+ if (ret)
+ return ret;
+#endif
+
return 0;
}
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 74de92ed13..1b428856b2 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -51,4 +51,47 @@ void handle_ipi(ulong hart);
*/
int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait);
+/**
+ * riscv_init_ipi() - Initialize inter-process interrupt (IPI) driver
+ *
+ * Platform code must provide this function. This function is called once after
+ * the cpu driver is initialized. No other riscv_*_ipi() calls will be made
+ * before this function is called.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int riscv_init_ipi(void);
+
+/**
+ * riscv_send_ipi() - Send inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of receiving hart
+ * @return 0 if OK, -ve on error
+ */
+int riscv_send_ipi(int hart);
+
+/**
+ * riscv_clear_ipi() - Clear inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of hart to be cleared
+ * @return 0 if OK, -ve on error
+ */
+int riscv_clear_ipi(int hart);
+
+/**
+ * riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of hart to be checked
+ * @pending: Pointer to variable with result of the check,
+ * 1 if IPI is pending, 0 otherwise
+ * @return 0 if OK, -ve on error
+ */
+int riscv_get_ipi(int hart, int *pending);
+
#endif
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 20529ab3eb..5cf29df670 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -30,20 +30,6 @@
#define SEND_IPI_TO_HART(hart) (0x80 >> (hart))
DECLARE_GLOBAL_DATA_PTR;
-static int init_plic(void);
-
-#define PLIC_BASE_GET(void)\
- do {\
- long *ret; \
- \
- if (!gd->arch.plic) { \
- ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
- if (IS_ERR(ret))\
- return PTR_ERR(ret);\
- gd->arch.plic = ret;\
- init_plic();\
- } \
- } while (0)
static int enable_ipi(int hart)
{
@@ -93,13 +79,21 @@ static int init_plic(void)
return -ENODEV;
}
+int riscv_init_ipi(void)
+{
+ long *ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
+
+ if (IS_ERR(ret))
+ return PTR_ERR(ret);
+ gd->arch.plic = ret;
+
+ return init_plic();
+}
+
int riscv_send_ipi(int hart)
{
- unsigned int ipi;
+ unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
- PLIC_BASE_GET();
-
- ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
gd->arch.boot_hart));
@@ -110,8 +104,6 @@ int riscv_clear_ipi(int hart)
{
u32 source_id;
- PLIC_BASE_GET();
-
source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
writel(source_id, (void __iomem *)CLAIM_
[PATCH v9 14/21] riscv: Clean up IPI initialization code
The previous IPI code initialized the device whenever the first call was
made to a riscv_*_ipi function. This made it difficult to determine when
the IPI device was initialized. This patch introduces a new function
riscv_init_ipi. It is called once during arch_cpu_init_dm. Before this
point, no riscv_*_ipi functions should be called.
Signed-off-by: Sean Anderson
Reviewed-by: Rick Chen
---
Changes in v9:
- Fix type of ret variable in riscv_ipi_init
Changes in v7:
- Split IPI clearing off into its own patch
Changes in v6:
- Fix some formatting
- Clear IPIs before enabling interrupts instead of using a ipi_ready flag
- Only print messages on error in smp code
Changes in v5:
- New
arch/riscv/cpu/cpu.c | 6
arch/riscv/include/asm/smp.h | 43 +++
arch/riscv/lib/andes_plic.c | 34 -
arch/riscv/lib/sbi_ipi.c | 5
arch/riscv/lib/sifive_clint.c | 33 +++--
arch/riscv/lib/smp.c | 56 ---
6 files changed, 90 insertions(+), 87 deletions(-)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index e457f6acbf..f851374255 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -96,6 +96,12 @@ int arch_cpu_init_dm(void)
csr_write(CSR_SATP, 0);
}
+#ifdef CONFIG_SMP
+ ret = riscv_init_ipi();
+ if (ret)
+ return ret;
+#endif
+
return 0;
}
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 74de92ed13..1b428856b2 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -51,4 +51,47 @@ void handle_ipi(ulong hart);
*/
int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait);
+/**
+ * riscv_init_ipi() - Initialize inter-process interrupt (IPI) driver
+ *
+ * Platform code must provide this function. This function is called once after
+ * the cpu driver is initialized. No other riscv_*_ipi() calls will be made
+ * before this function is called.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int riscv_init_ipi(void);
+
+/**
+ * riscv_send_ipi() - Send inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of receiving hart
+ * @return 0 if OK, -ve on error
+ */
+int riscv_send_ipi(int hart);
+
+/**
+ * riscv_clear_ipi() - Clear inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of hart to be cleared
+ * @return 0 if OK, -ve on error
+ */
+int riscv_clear_ipi(int hart);
+
+/**
+ * riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of hart to be checked
+ * @pending: Pointer to variable with result of the check,
+ * 1 if IPI is pending, 0 otherwise
+ * @return 0 if OK, -ve on error
+ */
+int riscv_get_ipi(int hart, int *pending);
+
#endif
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 20529ab3eb..5cf29df670 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -30,20 +30,6 @@
#define SEND_IPI_TO_HART(hart) (0x80 >> (hart))
DECLARE_GLOBAL_DATA_PTR;
-static int init_plic(void);
-
-#define PLIC_BASE_GET(void)\
- do {\
- long *ret; \
- \
- if (!gd->arch.plic) { \
- ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
- if (IS_ERR(ret))\
- return PTR_ERR(ret);\
- gd->arch.plic = ret;\
- init_plic();\
- } \
- } while (0)
static int enable_ipi(int hart)
{
@@ -93,13 +79,21 @@ static int init_plic(void)
return -ENODEV;
}
+int riscv_init_ipi(void)
+{
+ long *ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
+
+ if (IS_ERR(ret))
+ return PTR_ERR(ret);
+ gd->arch.plic = ret;
+
+ return init_plic();
+}
+
int riscv_send_ipi(int hart)
{
- unsigned int ipi;
+ unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
- PLIC_BASE_GET();
-
- ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
gd->arch.boot_hart));
@@ -110,8 +104,6 @@ int riscv_clear_ipi(int hart)
{
u32 source_id;
- PLIC_BASE_GET();
-
source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
writel(source_id, (void __iomem *)CLAIM_
