Re: [U-Boot] [PATCH][v2] powerpc/t1040qds: Add Video - HDMI support
On 02/26/2014 02:41 AM, Priyanka Jain wrote: T1040 has internal display interface unit (DIU) for driving video. T1040QDS supports video mode via -LCD using TI enconder -HDMI type interface via HDMI encoder Chrontel, CH7301C encoder which is I2C programmable is used as HDMI connector on T1040QDS. This patch add support to -enable Video interface for T1040QDS -route qixis multiplexing to enable DIU-HDMI interface on board -program DIU pixel clock gerenartor for T1040 -program HDMI encoder via I2C on board Signed-off-by: Priyanka Jain priyanka.j...@freescale.com --- Changes for v2: Fix compilation warnings Depends on http://patchwork.ozlabs.org/patch/315294/ Applied to u-boot-mpc85xx/master. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH][v2] powerpc/t1040qds: Add Video - HDMI support
T1040 has internal display interface unit (DIU) for driving video.
T1040QDS supports video mode via
-LCD using TI enconder
-HDMI type interface via HDMI encoder
Chrontel, CH7301C encoder which is I2C programmable is used as
HDMI connector on T1040QDS.
This patch add support to
-enable Video interface for T1040QDS
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1040
-program HDMI encoder via I2C on board
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2: Fix compilation warnings
Depends on http://patchwork.ozlabs.org/patch/315294/
board/freescale/t1040qds/Makefile |1 +
board/freescale/t1040qds/diu.c| 215 +
board/freescale/t1040qds/t1040qds.h |1 +
board/freescale/t1040qds/t1040qds_qixis.h | 12 ++
include/configs/T1040QDS.h| 27 -
5 files changed, 255 insertions(+), 1 deletions(-)
create mode 100644 board/freescale/t1040qds/diu.c
diff --git a/board/freescale/t1040qds/Makefile
b/board/freescale/t1040qds/Makefile
index c7470d7..19ed21b 100644
--- a/board/freescale/t1040qds/Makefile
+++ b/board/freescale/t1040qds/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_PCI) += pci.o
obj-y += law.o
obj-y += tlb.o
obj-y += eth.o
+obj-y += diu.o
diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c
new file mode 100644
index 000..ffd074b
--- /dev/null
+++ b/board/freescale/t1040qds/diu.c
@@ -0,0 +1,215 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Priyanka Jain priyanka.j...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include command.h
+#include linux/ctype.h
+#include asm/io.h
+#include stdio_dev.h
+#include video_fb.h
+#include fsl_diu_fb.h
+#include ../common/qixis.h
+#include t1040qds.h
+#include t1040qds_qixis.h
+#include i2c.h
+
+
+#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F
+#define I2C_DVI_PLL_CHARGE_CNTL_REG0x33
+#define I2C_DVI_PLL_DIVIDER_REG0x34
+#define I2C_DVI_PLL_SUPPLY_CNTL_REG0x35
+#define I2C_DVI_PLL_FILTER_REG 0x36
+#define I2C_DVI_TEST_PATTERN_REG 0x48
+#define I2C_DVI_POWER_MGMT_REG 0x49
+#define I2C_DVI_LOCK_STATE_REG 0x4D
+#define I2C_DVI_SYNC_POLARITY_REG 0x56
+
+/*
+ * Set VSYNC/HSYNC to active high. This is polarity of sync signals
+ * from DIU-DVI. The DIU default is active igh, so DVI is set to
+ * active high.
+ */
+#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98
+
+#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06
+#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26
+#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0
+#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08
+#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16
+#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60
+
+/* Clear test pattern */
+#define I2C_DVI_TEST_PATTERN_VAL 0x18
+/* Exit Power-down mode */
+#define I2C_DVI_POWER_MGMT_VAL 0xC0
+
+/* Monitor polarity is handled via DVI Sync Polarity Register */
+#define I2C_DVI_SYNC_POLARITY_VAL 0x00
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register. So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F 0x1000
+#define AD_ALPHA_C_SHIFT 25
+#define AD_BLUE_C_SHIFT23
+#define AD_GREEN_C_SHIFT 21
+#define AD_RED_C_SHIFT 19
+#define AD_PIXEL_S_SHIFT 16
+#define AD_COMP_3_SHIFT12
+#define AD_COMP_2_SHIFT8
+#define AD_COMP_1_SHIFT4
+#define AD_COMP_0_SHIFT0
+
+/* Programming of HDMI Chrontel CH7301 connector */
+int diu_set_dvi_encoder(unsigned int pixclock)
+{
+ int ret;
+ u8 temp;
+ select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
+
+ temp = I2C_DVI_TEST_PATTERN_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
+ temp, 1);
+ if (ret) {
+ puts(I2C: failed to select proper dvi test pattern\n);
+ return ret;
+ }
+ temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
+ 1, temp, 1);
+ if (ret) {
+ puts(I2C: failed to select dvi input data format\n);
+ return ret;
+ }
+
+ /* Set Sync polarity register */
+ temp = I2C_DVI_SYNC_POLARITY_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
+ temp, 1);
+ if (ret) {
+ puts(I2C: failed to select dvi syc polarity\n);
+
[U-Boot] [PATCH][v2] powerpc/t1040qds: Add Video - HDMI support
T1040 has internal display interface unit (DIU) for driving video.
T1040QDS supports video mode via
-LCD using TI enconder
-HDMI type interface via HDMI encoder
Chrontel, CH7301C encoder which is I2C programmable is used as
HDMI connector on T1040QDS.
This patch add support to
-enable Video interface for T1040QDS
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1040
-program HDMI encoder via I2C on board
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v2: Fix compilation warnings
board/freescale/t1040qds/Makefile |1 +
board/freescale/t1040qds/diu.c| 215 +
board/freescale/t1040qds/t1040qds.h |1 +
board/freescale/t1040qds/t1040qds_qixis.h | 12 ++
include/configs/T1040QDS.h| 27 -
5 files changed, 255 insertions(+), 1 deletions(-)
create mode 100644 board/freescale/t1040qds/diu.c
diff --git a/board/freescale/t1040qds/Makefile
b/board/freescale/t1040qds/Makefile
index c7470d7..19ed21b 100644
--- a/board/freescale/t1040qds/Makefile
+++ b/board/freescale/t1040qds/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_PCI) += pci.o
obj-y += law.o
obj-y += tlb.o
obj-y += eth.o
+obj-y += diu.o
diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c
new file mode 100644
index 000..ffd074b
--- /dev/null
+++ b/board/freescale/t1040qds/diu.c
@@ -0,0 +1,215 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Priyanka Jain priyanka.j...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include command.h
+#include linux/ctype.h
+#include asm/io.h
+#include stdio_dev.h
+#include video_fb.h
+#include fsl_diu_fb.h
+#include ../common/qixis.h
+#include t1040qds.h
+#include t1040qds_qixis.h
+#include i2c.h
+
+
+#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F
+#define I2C_DVI_PLL_CHARGE_CNTL_REG0x33
+#define I2C_DVI_PLL_DIVIDER_REG0x34
+#define I2C_DVI_PLL_SUPPLY_CNTL_REG0x35
+#define I2C_DVI_PLL_FILTER_REG 0x36
+#define I2C_DVI_TEST_PATTERN_REG 0x48
+#define I2C_DVI_POWER_MGMT_REG 0x49
+#define I2C_DVI_LOCK_STATE_REG 0x4D
+#define I2C_DVI_SYNC_POLARITY_REG 0x56
+
+/*
+ * Set VSYNC/HSYNC to active high. This is polarity of sync signals
+ * from DIU-DVI. The DIU default is active igh, so DVI is set to
+ * active high.
+ */
+#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98
+
+#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06
+#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26
+#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0
+#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08
+#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16
+#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60
+
+/* Clear test pattern */
+#define I2C_DVI_TEST_PATTERN_VAL 0x18
+/* Exit Power-down mode */
+#define I2C_DVI_POWER_MGMT_VAL 0xC0
+
+/* Monitor polarity is handled via DVI Sync Polarity Register */
+#define I2C_DVI_SYNC_POLARITY_VAL 0x00
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register. So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F 0x1000
+#define AD_ALPHA_C_SHIFT 25
+#define AD_BLUE_C_SHIFT23
+#define AD_GREEN_C_SHIFT 21
+#define AD_RED_C_SHIFT 19
+#define AD_PIXEL_S_SHIFT 16
+#define AD_COMP_3_SHIFT12
+#define AD_COMP_2_SHIFT8
+#define AD_COMP_1_SHIFT4
+#define AD_COMP_0_SHIFT0
+
+/* Programming of HDMI Chrontel CH7301 connector */
+int diu_set_dvi_encoder(unsigned int pixclock)
+{
+ int ret;
+ u8 temp;
+ select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
+
+ temp = I2C_DVI_TEST_PATTERN_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
+ temp, 1);
+ if (ret) {
+ puts(I2C: failed to select proper dvi test pattern\n);
+ return ret;
+ }
+ temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
+ 1, temp, 1);
+ if (ret) {
+ puts(I2C: failed to select dvi input data format\n);
+ return ret;
+ }
+
+ /* Set Sync polarity register */
+ temp = I2C_DVI_SYNC_POLARITY_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
+ temp, 1);
+ if (ret) {
+ puts(I2C: failed to select dvi syc polarity\n);
+ return ret;
+ }
+
+ /* Set PLL
