Re: [U-Boot] [PATCH] ARM: tegra20: Add a missing entry in the pullid enum
On Wed, 15 Jan 2014 11:36:03 -0700 Stephen Warren swar...@wwwdotorg.org wrote: On 01/15/2014 07:55 AM, Alban Bedel wrote: It seems two entries were merged in one when this file has been created. The GPSLXAU entries is obviously a mix of GPU and SLXA which are next to each other according to the datasheet. Moreover it can be noticed because the APB_MISC_PP_PULLUPDOWN_REG_B_0 register only have 15 entries instead of 16. Also fix the pin group descriptions that were using these buggy entries. In particular SLXA that needed to used CRTP to actually write the SLXA register. This does appear to match the kernel's pinctrl driver, so, Acked-by: Stephen Warren swar...@nvidia.com I wonder how many more similar issues there are. Did you check the whole file for this kind of issue, or just debug a problem with one particular pin/group? I found this while trying to get the internal pull up enabled on UARTD. Afterwards I checked the whole enum and the table but everything else seems to be correct. Alban ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ARM: tegra20: Add a missing entry in the pullid enum
It seems two entries were merged in one when this file has been
created. The GPSLXAU entries is obviously a mix of GPU and SLXA which
are next to each other according to the datasheet. Moreover it can be
noticed because the APB_MISC_PP_PULLUPDOWN_REG_B_0 register only have
15 entries instead of 16.
Also fix the pin group descriptions that were using these buggy
entries. In particular SLXA that needed to used CRTP to actually
write the SLXA register.
Signed-off-by: Alban Bedel alban.be...@avionic-design.de
---
arch/arm/cpu/tegra20-common/pinmux.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/tegra20-common/pinmux.c
b/arch/arm/cpu/tegra20-common/pinmux.c
index a65e991..5c80ed9 100644
--- a/arch/arm/cpu/tegra20-common/pinmux.c
+++ b/arch/arm/cpu/tegra20-common/pinmux.c
@@ -190,7 +190,8 @@ enum pmux_pullid {
PUCTL_SPDI,
PUCTL_SPDO,
- PUCTL_GPSLXAU,
+ PUCTL_GPU,
+ PUCTL_SLXA,
PUCTL_CRTP,
PUCTL_SLXC,
PUCTL_SLXD,
@@ -333,8 +334,7 @@ const struct tegra_pingroup_desc
tegra_soc_pingroups[PINGRP_COUNT] = {
PIN(DTD, VI,RSVD, SDIO2, VI,RSVD,RSVD1),
PIN(DTE, VI,RSVD, RSVD, VI,SPI1,RSVD1),
- PINP(GPU, UART, PWM,UARTA, GMI, RSVD,RSVD4,
- GPSLXAU),
+ PIN(GPU, UART, PWM,UARTA, GMI, RSVD,RSVD4),
PIN(GPV, SD,PCIE, RSVD, RSVD, RSVD,PCIE),
PIN(I2CP, SYS, I2C,RSVD, RSVD, RSVD,RSVD4),
PIN(IRTX, UART, UARTA, UARTB, GMI, SPI4,UARTB),
@@ -356,7 +356,7 @@ const struct tegra_pingroup_desc
tegra_soc_pingroups[PINGRP_COUNT] = {
PIN(SDC, SD,PWM,TWC,SDIO3, SPI3,TWC),
PIN(SDD, SD,UARTA, PWM,SDIO3, SPI3,PWM),
PIN_RESERVED,
- PINP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2,PCIE, CRTP),
+ PIN(SLXA, SD,PCIE, SPI4, SDIO3, SPI2,PCIE),
PIN(SLXC, SD,SPDIF, SPI4, SDIO3, SPI2,SPI4),
PIN(SLXD, SD,SPDIF, SPI4, SDIO3, SPI2,SPI4),
PIN(SLXK, SD,PCIE, SPI4, SDIO3, SPI2,PCIE),
--
1.8.5.2
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Re: [U-Boot] [PATCH] ARM: tegra20: Add a missing entry in the pullid enum
On 01/15/2014 07:55 AM, Alban Bedel wrote: It seems two entries were merged in one when this file has been created. The GPSLXAU entries is obviously a mix of GPU and SLXA which are next to each other according to the datasheet. Moreover it can be noticed because the APB_MISC_PP_PULLUPDOWN_REG_B_0 register only have 15 entries instead of 16. Also fix the pin group descriptions that were using these buggy entries. In particular SLXA that needed to used CRTP to actually write the SLXA register. This does appear to match the kernel's pinctrl driver, so, Acked-by: Stephen Warren swar...@nvidia.com I wonder how many more similar issues there are. Did you check the whole file for this kind of issue, or just debug a problem with one particular pin/group? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
