Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Marek Vasut]

On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> Updated pinmux group MIXED1IO[15-20] for QSPI.
> Updated QSPI clock.
> 
> Signed-off-by: shengjiangwu 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Dinh Nguyen 
> Cc: Pavel Machek 
> Cc: Marek Vasut 
> Cc: Stefan Roese 

Applied, thanks.

I will push your patches to [1] in a few hours, can you try and see if the
CV SOCDK works fine for you? Thanks

[1] http://git.denx.de/?p=u-boot/u-boot-
socfpga.git;a=shortlog;h=refs/heads/master

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Marek Vasut]

On Wednesday, December 23, 2015 at 02:25:29 AM, 圣江 吴 wrote:
> On Dec 22, 2015, at 05:22 PM, 圣江 吴  wrote:
> 
> 
> 
> On Dec 22, 2015, at 12:33 PM, Marek Vasut  wrote:
> 
> On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
> 
> On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > Updated QSPI clock.
> > 
> > Signed-off-by: shengjiangwu 
> > Cc: Chin Liang See 
> > Cc: Dinh Nguyen 
> > Cc: Dinh Nguyen 
> > Cc: Pavel Machek 
> > Cc: Marek Vasut 
> > Cc: Stefan Roese 
> 
> Applied, thanks.
> 
> I will push your patches to [1] in a few hours, can you try and see if the
> CV SOCDK works fine for you? Thanks
> 
> [1] http://git.denx.de/?p=u-boot/u-boot-
> socfpga.git;a=shortlog;h=refs/heads/master
> 
> Pushed. Please let me know how SoCDK works for you now and if there are
> still some problems.
> 
> 
> Best regards,
> Marek Vasut
> 
> 
> Hi Marek,
> 
> Thank you for your help, I tested the master branch, emac1 and QSPI
> works. Below is log.
> 
> Best Regards,
> ShengjiangWu
> 
> => reset
> resetting ...
> 
> U-Boot SPL 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52)
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
> drivers/ddr/altera/sequencer.c: Calibration complete
> Trying to boot from MMC
> 
> 
> U-Boot 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52 +0800)
> 
> CPU: Altera SoCFPGA Platform
> FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
> BOOT: SD/MMC External Transceiver (1.8V)
> Watchdog enabled
> I2C: ready
> DRAM: 1 GiB
> MMC: dwmmc0@ff704000: 0
> *** Warning - bad CRC, using default environment
> 
> In: serial
> Out: serial
> Err: serial
> Model: Altera SOCFPGA Cyclone V SoC Development Kit
> Net:
> Error: ethernet@ff702000 address not set.
> No ethernet found.
> Hit any key to stop autoboot: 0
> => env default -a
> ## Resetting to default environment
> => setenv netmask 255.255.254.0
> => setenv gatewayip 128.224.98.1
> => setenv ipaddr 128.224.98.85
> => setenv serverip 128.224.99.137
> => setenv ethaddr 00:04:9f:13:57:b4
> => saveenv
> Saving Environment to MMC...
> Writing to MMC(0)... done
> => reset
> resetting ...
> 
> U-Boot SPL 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52)
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
> drivers/ddr/altera/sequencer.c: Calibration complete
> Trying to boot from MMC
> 
> 
> U-Boot 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52 +0800)
> 
> CPU: Altera SoCFPGA Platform
> FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
> BOOT: SD/MMC External Transceiver (1.8V)
> Watchdog enabled
> I2C: ready
> DRAM: 1 GiB
> MMC: dwmmc0@ff704000: 0
> In: serial
> Out: serial
> Err: serial
> Model: Altera SOCFPGA Cyclone V SoC Development Kit
> Net: eth0: ethernet@ff702000
> Hit any key to stop autoboot: 0
> => tftp 0x800 /tftpboot/altera/uVxWorks
> Speed: 100, full duplex
> Using ethernet@ff702000 device
> TFTP from server 128.224.99.137; our IP address is 128.224.98.85
> Filename '/tftpboot/altera/uVxWorks'.
> Load address: 0x800
> Loading: #
> #
> #
> #
> #
> #
> 
> 3.3 MiB/s
> done
> Bytes transferred = 6418496 (61f040 hex)
> => sf probe
> SF: Detected N25Q1024 with page size 256 Bytes, erase size 64 KiB, total
> 128 MiB => sf read 0x700 0 0x6
> device 0 offset 0x0, size 0x6
> SF: 393216 bytes @ 0x0 Read: OK
> => md 0x700
> 0700: ea1a e59ff014 e59ff014 e59ff014 
> 0710: e59ff014 e59ff014 e59ff014 e59ff014 
> 0720: 0020 0024 0028 002c ...$...(...,...
> 0730: 0030 0100 0038 12345678 0...8...xV4.
> 0740: 31305341 2e16 0139 ea07 AS01..9.
> 0750: 0140 b854 b854 b900 @...T...T...
> 0760: b854 0badc0de 0badc0de 0badc0de T...
> 0770: eb40 e10f e3c0001f e38000d3 @...
> 0780: e129f000 ee110f10 e3c00a02 ee010f10 ..).
> 0790: e59f00a8 ee0c0f10 eb08 eb15 
> 07a0: eb000690 ee070f15 ee070f9a ee070f95 
> 07b0: e59f0088 ee0c0f10 e12fff1e e12fff1e ../.../.
> 07c0: e3a0 ee080f17 ee070f15 ee070fd5 
> 07d0: ee070f9a 

Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Chin Liang See]

On Wed, 2015-12-23 at 10:29 +0800, Chin Liang See wrote:
> On Wed, 2015-12-23 at 03:27 +0100, Marek Vasut wrote:
> > On Wednesday, December 23, 2015 at 03:26:07 AM, 圣江 吴 wrote:

[..]

> > > 
> > > Hi Marek,
> > > 
> > > Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2,
> > > then usb
> > > works,
> > > 
> > > => usb start
> > > starting USB...
> > > USB0: Core Release: 2.93a
> > > scanning bus 0 for devices... 2 USB Device(s) found
> > > => usb tree
> > > USB device tree:
> > > 1 Hub (480 Mb/s, 0mA)
> > > 
> > > > U-Boot Root Hub
> > > 
> > > +-2 Mass Storage (480 Mb/s, 98mA)
> > > Generic USB Storage 0272
> > 
> > Cool, thanks! Patch please ;-)
> 
> Nice, guess Altera email is very slow
> 

Yup, it work for me too with the pinmux change and dcache on.

U-Boot SPL 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
drivers/ddr/altera/sequencer.c: Calibration complete
Trying to boot from MMC
spl: mmc boot mode: raw
 
 
U-Boot 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29 +0800)
 
CPU:   Altera SoCFPGA Platform
FPGA:  Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT:  SD/MMC External Transceiver (1.8V)
   Watchdog enabled
I2C:   ready
DRAM:  1 GiB
MMC:   dwmmc0@ff704000: 0
*** Warning - bad CRC, using default environment
 
In:serial
Out:   serial
Err:   serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net:
Error: ethernet@ff702000 address not set.
No ethernet found.
Hit any key to stop autoboot:  0
=> dcache
Data (writethrough) Cache is ON
=> usb reset
resetting USB...
USB0:   Core Release: 2.93a
scanning bus 0 for devices... 2 USB Device(s) found
=> usb info
1: Hub,  USB Revision 1.10
-  U-Boot Root Hub
- Class: Hub
- PacketSize: 8  Configurations: 1
- Vendor: 0x  Product 0x Version 0.0
   Configuration: 1
   - Interfaces: 1 Self Powered 0mA
 Interface: 0
 - Alternate Setting 0, Endpoints: 1
 - Class Hub
 - Endpoint 1 In Interrupt MaxPacket 2 Interval 255ms
 
2: Mass Storage,  USB Revision 2.0
-  USB DISK 2.0 0781076602A6
- Class: (from Interface) Mass Storage
- PacketSize: 64  Configurations: 1
- Vendor: 0x13fe  Product 0x1e00 Version 1.16
   Configuration: 1
   - Interfaces: 1 Bus Powered 200mA
 Interface: 0
 - Alternate Setting 0, Endpoints: 2
 - Class Mass Storage, Transp. SCSI, Bulk only
 - Endpoint 1 In Bulk MaxPacket 512
 - Endpoint 2 Out Bulk MaxPacket 512

Thanks
Chin Liang

> Thanks
> Chin Liang
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Marek Vasut]

On Wednesday, December 23, 2015 at 02:22:49 AM, 圣江 吴 wrote:
> On Dec 22, 2015, at 12:33 PM, Marek Vasut  wrote:
> 
> On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
> 
> On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > Updated QSPI clock.
> > 
> > Signed-off-by: shengjiangwu 
> > Cc: Chin Liang See 
> > Cc: Dinh Nguyen 
> > Cc: Dinh Nguyen 
> > Cc: Pavel Machek 
> > Cc: Marek Vasut 
> > Cc: Stefan Roese 
> 
> Applied, thanks.
> 
> I will push your patches to [1] in a few hours, can you try and see if the
> CV SOCDK works fine for you? Thanks
> 
> [1] http://git.denx.de/?p=u-boot/u-boot-
> socfpga.git;a=shortlog;h=refs/heads/master
> 
> Pushed. Please let me know how SoCDK works for you now and if there are
> still some problems.
> 
> 
> Best regards,
> Marek Vasut
> 
> 
> Hi Marek,
> 
> Thank you for your help, I tested the master branch, emac1 and QSPI
> works. Below is log.

Good! so we're happy ? Can you give USB a spin too? I think it might have
some issues and I don't have the necessary cable here.

[...]

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Marek Vasut]

On Wednesday, December 23, 2015 at 03:02:10 AM, ShengjiangWu wrote:
> > -Original Message-
> > From: Marek Vasut [mailto:ma...@denx.de]
> > Sent: Wednesday, December 23, 2015 9:25 AM
> > To: 圣江 吴
> > Cc: u-boot@lists.denx.de; cl...@altera.com;
> > dingu...@opensource.altera.com; dinh.li...@gmail.com; pa...@denx.de;
> > s...@denx.de Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on
> > socdk board
> > 
> > On Wednesday, December 23, 2015 at 02:22:49 AM, 圣江 吴 wrote:
> > > On Dec 22, 2015, at 12:33 PM, Marek Vasut  wrote:
> > > 
> > > On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
> > > 
> > > On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > > > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > > > Updated QSPI clock.
> > > > 
> > > > Signed-off-by: shengjiangwu 
> > > > Cc: Chin Liang See 
> > > > Cc: Dinh Nguyen 
> > > > Cc: Dinh Nguyen 
> > > > Cc: Pavel Machek 
> > > > Cc: Marek Vasut 
> > > > Cc: Stefan Roese 
> > > 
> > > Applied, thanks.
> > > 
> > > I will push your patches to [1] in a few hours, can you try and see if
> > > the CV SOCDK works fine for you? Thanks
> > > 
> > > [1] http://git.denx.de/?p=u-boot/u-boot-
> > > socfpga.git;a=shortlog;h=refs/heads/master
> > > 
> > > Pushed. Please let me know how SoCDK works for you now and if there
> > > are still some problems.
> > > 
> > > 
> > > Best regards,
> > > Marek Vasut
> > > 
> > > 
> > > Hi Marek,
> > > 
> > > Thank you for your help, I tested the master branch, emac1 and QSPI
> > > works. Below is log.
> > 
> > Good! so we're happy ? Can you give USB a spin too? I think it might have
> > some issues and I don't have the necessary cable here.
> > 
> > [...]
> > 
> > Best regards,
> > Marek Vasut
> 
> Hi Marek,
> 
> Yes, emac1 and qspi are working now. I'm afraid USB is not working,
> 
> => usb reset
> resetting USB...
> USB0:   Core Release: 2.93a
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> scanning bus 0 for devices... 1 USB Device(s) found
> => usb tree
> USB device tree:
>   1  Hub (480 Mb/s, 0mA)
>   U-Boot Root Hub

Hm, darn. Can you or Chin check it ? It's either pinmux or wrong USB node
in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Chin Liang See]

On Wed, 2015-12-23 at 03:07 +0100, Marek Vasut wrote:
> On Wednesday, December 23, 2015 at 03:02:10 AM, ShengjiangWu wrote:

[..]

> > Hi Marek,
> > 
> > Yes, emac1 and qspi are working now. I'm afraid USB is not working,
> > 
> > => usb reset
> > resetting USB...
> > USB0:   Core Release: 2.93a
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > scanning bus 0 for devices... 1 USB Device(s) found
> > => usb tree
> > USB device tree:
> >   1  Hub (480 Mb/s, 0mA)
> >   U-Boot Root Hub
> 
> Hm, darn. Can you or Chin check it ? It's either pinmux or wrong USB
> node
> in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .

I am still setting up the SPL into SD card. In the mean time, I believe
the error come from pinmux. Shengjiang, can you try out below change?

diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h
b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index 06783dc..fb8648b 100644
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -8,20 +8,20 @@
#define __SOCFPGA_PINMUX_CONFIG_H__
 
const u8 sys_mgr_init_table[] = {
-   3, /* EMACIO0 */
-   3, /* EMACIO1 */
-   3, /* EMACIO2 */
-   3, /* EMACIO3 */
-   3, /* EMACIO4 */
-   3, /* EMACIO5 */
-   3, /* EMACIO6 */
-   3, /* EMACIO7 */
-   3, /* EMACIO8 */
-   3, /* EMACIO9 */
-   3, /* EMACIO10 */
-   3, /* EMACIO11 */
-   3, /* EMACIO12 */
-   3, /* EMACIO13 */
+   0, /* EMACIO0 */
+   2, /* EMACIO1 */
+   2, /* EMACIO2 */
+   2, /* EMACIO3 */
+   2, /* EMACIO4 */
+   2, /* EMACIO5 */
+   2, /* EMACIO6 */
+   2, /* EMACIO7 */
+   2, /* EMACIO8 */
+   0, /* EMACIO9 */
+   2, /* EMACIO10 */
+   2, /* EMACIO11 */
+   2, /* EMACIO12 */
+   2, /* EMACIO13 */
0, /* EMACIO14 */
0, /* EMACIO15 */
0, /* EMACIO16 */

Thanks
Chin Liang
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Marek Vasut]

On Wednesday, December 23, 2015 at 03:26:07 AM, 圣江 吴 wrote:
> > From: Marek Vasut
> > Date: 2015-12-23 10:07
> > To: ShengjiangWu
> > CC: u-boot; clsee; dinguyen; dinh.linux; pavel; sr
> > Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
> > 
> > On Wednesday, December 23, 2015 at 03:02:10 AM, ShengjiangWu wrote:
> > > > -Original Message-
> > > > From: Marek Vasut [mailto:ma...@denx.de]
> > > > Sent: Wednesday, December 23, 2015 9:25 AM
> > > > To: 圣江 吴
> > > > Cc: u-boot@lists.denx.de; cl...@altera.com;
> > > > dingu...@opensource.altera.com; dinh.li...@gmail.com; pa...@denx.de;
> > > > s...@denx.de Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work
> > > > on socdk board
> > > > 
> > > > On Wednesday, December 23, 2015 at 02:22:49 AM, 圣江 吴 wrote:
> > > > > On Dec 22, 2015, at 12:33 PM, Marek Vasut  wrote:
> > > > > 
> > > > > On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
> > > > > 
> > > > > On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > > > > > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > > > > > Updated QSPI clock.
> > > > > > 
> > > > > > Signed-off-by: shengjiangwu 
> > > > > > Cc: Chin Liang See 
> > > > > > Cc: Dinh Nguyen 
> > > > > > Cc: Dinh Nguyen 
> > > > > > Cc: Pavel Machek 
> > > > > > Cc: Marek Vasut 
> > > > > > Cc: Stefan Roese 
> > > > > 
> > > > > Applied, thanks.
> > > > > 
> > > > > I will push your patches to [1] in a few hours, can you try and see
> > > > > if the CV SOCDK works fine for you? Thanks
> > > > > 
> > > > > [1] http://git.denx.de/?p=u-boot/u-boot-
> > > > > socfpga.git;a=shortlog;h=refs/heads/master
> > > > > 
> > > > > Pushed. Please let me know how SoCDK works for you now and if there
> > > > > are still some problems.
> > > > > 
> > > > > 
> > > > > Best regards,
> > > > > Marek Vasut
> > > > > 
> > > > > 
> > > > > Hi Marek,
> > > > > 
> > > > > Thank you for your help, I tested the master branch, emac1 and QSPI
> > > > > works. Below is log.
> > > > 
> > > > Good! so we're happy ? Can you give USB a spin too? I think it might
> > > > have some issues and I don't have the necessary cable here.
> > > > 
> > > > [...]
> > > > 
> > > > Best regards,
> > > > Marek Vasut
> > > 
> > > Hi Marek,
> > > 
> > > Yes, emac1 and qspi are working now. I'm afraid USB is not working,
> > > 
> > > => usb reset
> > > resetting USB...
> > > USB0: Core Release: 2.93a
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > scanning bus 0 for devices... 1 USB Device(s) found
> > > => usb tree
> > > USB device tree:
> > > 1 Hub (480 Mb/s, 0mA)
> > > U-Boot Root Hub
> > 
> > Hm, darn. Can you or Chin check it ? It's either pinmux or wrong USB node
> > in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .
> 
> Hi Marek,
> 
> Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2, then usb
> works,
> 
> => usb start
> starting USB...
> USB0: Core Release: 2.93a
> scanning bus 0 for devices... 2 USB Device(s) found
> => usb tree
> USB device tree:
> 1 Hub (480 Mb/s, 0mA)
> 
> | U-Boot Root Hub
> 
> +-2 Mass Storage (480 Mb/s, 98mA)
> Generic USB Storage 0272

Cool, thanks! Patch please ;-)
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Marek Vasut]

On Wednesday, December 23, 2015 at 03:38:25 AM, Chin Liang See wrote:
> On Wed, 2015-12-23 at 10:29 +0800, Chin Liang See wrote:
> > On Wed, 2015-12-23 at 03:27 +0100, Marek Vasut wrote:
> > > On Wednesday, December 23, 2015 at 03:26:07 AM, 圣江 吴 wrote:
> [..]
> 
> > > > Hi Marek,
> > > > 
> > > > Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2,
> > > > then usb
> > > > works,
> > > > 
> > > > => usb start
> > > > starting USB...
> > > > USB0: Core Release: 2.93a
> > > > scanning bus 0 for devices... 2 USB Device(s) found
> > > > => usb tree
> > > > USB device tree:
> > > > 1 Hub (480 Mb/s, 0mA)
> > > > 
> > > > > U-Boot Root Hub
> > > > 
> > > > +-2 Mass Storage (480 Mb/s, 98mA)
> > > > Generic USB Storage 0272
> > > 
> > > Cool, thanks! Patch please ;-)
> > 
> > Nice, guess Altera email is very slow
> 
> Yup, it work for me too with the pinmux change and dcache on.
> 
> U-Boot SPL 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29)
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
> drivers/ddr/altera/sequencer.c: Calibration complete
> Trying to boot from MMC
> spl: mmc boot mode: raw
> 
> 
> U-Boot 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29 +0800)
> 
> CPU:   Altera SoCFPGA Platform
> FPGA:  Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
> BOOT:  SD/MMC External Transceiver (1.8V)
>Watchdog enabled
> I2C:   ready
> DRAM:  1 GiB
> MMC:   dwmmc0@ff704000: 0
> *** Warning - bad CRC, using default environment
> 
> In:serial
> Out:   serial
> Err:   serial
> Model: Altera SOCFPGA Cyclone V SoC Development Kit
> Net:
> Error: ethernet@ff702000 address not set.
> No ethernet found.
> Hit any key to stop autoboot:  0
> => dcache
> Data (writethrough) Cache is ON
> => usb reset
> resetting USB...
> USB0:   Core Release: 2.93a
> scanning bus 0 for devices... 2 USB Device(s) found
> => usb info
> 1: Hub,  USB Revision 1.10
> -  U-Boot Root Hub
> - Class: Hub
> - PacketSize: 8  Configurations: 1
> - Vendor: 0x  Product 0x Version 0.0
>Configuration: 1
>- Interfaces: 1 Self Powered 0mA
>  Interface: 0
>  - Alternate Setting 0, Endpoints: 1
>  - Class Hub
>  - Endpoint 1 In Interrupt MaxPacket 2 Interval 255ms
> 
> 2: Mass Storage,  USB Revision 2.0
> -  USB DISK 2.0 0781076602A6
> - Class: (from Interface) Mass Storage
> - PacketSize: 64  Configurations: 1
> - Vendor: 0x13fe  Product 0x1e00 Version 1.16
>Configuration: 1
>- Interfaces: 1 Bus Powered 200mA
>  Interface: 0
>  - Alternate Setting 0, Endpoints: 2
>  - Class Mass Storage, Transp. SCSI, Bulk only
>  - Endpoint 1 In Bulk MaxPacket 512
>  - Endpoint 2 Out Bulk MaxPacket 512

Cool, I will pick the patch shortly.
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Chin Liang See]

On Wed, 2015-12-23 at 03:27 +0100, Marek Vasut wrote:
> On Wednesday, December 23, 2015 at 03:26:07 AM, 圣江 吴 wrote:
> > > From: Marek Vasut
> > > Date: 2015-12-23 10:07
> > > To: ShengjiangWu
> > > CC: u-boot; clsee; dinguyen; dinh.linux; pavel; sr
> > > Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk
> > > board
> > > 
> > > On Wednesday, December 23, 2015 at 03:02:10 AM, ShengjiangWu
> > > wrote:
> > > > > -Original Message-
> > > > > From: Marek Vasut [mailto:ma...@denx.de]
> > > > > Sent: Wednesday, December 23, 2015 9:25 AM
> > > > > To: 圣江 吴
> > > > > Cc: u-boot@lists.denx.de; cl...@altera.com;
> > > > > dingu...@opensource.altera.com; dinh.li...@gmail.com; 
> > > > > pa...@denx.de;
> > > > > s...@denx.de Subject: Re: [PATCH] arm: socfpga: Fix QSPI
> > > > > doesn't work
> > > > > on socdk board
> > > > > 
> > > > > On Wednesday, December 23, 2015 at 02:22:49 AM, 圣江 吴 wrote:
> > > > > > On Dec 22, 2015, at 12:33 PM, Marek Vasut 
> > > > > > wrote:
> > > > > > 
> > > > > > On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut
> > > > > > wrote:
> > > > > > 
> > > > > > On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu
> > > > > > wrote:
> > > > > > > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > > > > > > Updated QSPI clock.
> > > > > > > 
> > > > > > > Signed-off-by: shengjiangwu 
> > > > > > > Cc: Chin Liang See 
> > > > > > > Cc: Dinh Nguyen 
> > > > > > > Cc: Dinh Nguyen 
> > > > > > > Cc: Pavel Machek 
> > > > > > > Cc: Marek Vasut 
> > > > > > > Cc: Stefan Roese 
> > > > > > 
> > > > > > Applied, thanks.
> > > > > > 
> > > > > > I will push your patches to [1] in a few hours, can you try
> > > > > > and see
> > > > > > if the CV SOCDK works fine for you? Thanks
> > > > > > 
> > > > > > [1] http://git.denx.de/?p=u-boot/u-boot-
> > > > > > socfpga.git;a=shortlog;h=refs/heads/master
> > > > > > 
> > > > > > Pushed. Please let me know how SoCDK works for you now and
> > > > > > if there
> > > > > > are still some problems.
> > > > > > 
> > > > > > 
> > > > > > Best regards,
> > > > > > Marek Vasut
> > > > > > 
> > > > > > 
> > > > > > Hi Marek,
> > > > > > 
> > > > > > Thank you for your help, I tested the master branch, emac1
> > > > > > and QSPI
> > > > > > works. Below is log.
> > > > > 
> > > > > Good! so we're happy ? Can you give USB a spin too? I think
> > > > > it might
> > > > > have some issues and I don't have the necessary cable here.
> > > > > 
> > > > > [...]
> > > > > 
> > > > > Best regards,
> > > > > Marek Vasut
> > > > 
> > > > Hi Marek,
> > > > 
> > > > Yes, emac1 and qspi are working now. I'm afraid USB is not
> > > > working,
> > > > 
> > > > => usb reset
> > > > resetting USB...
> > > > USB0: Core Release: 2.93a
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > scanning bus 0 for devices... 1 USB Device(s) found
> > > > => usb tree
> > > > USB device tree:
> > > > 1 Hub (480 Mb/s, 0mA)
> > > > U-Boot Root Hub
> > > 
> > > Hm, darn. Can you or Chin check it ? It's either pinmux or wrong
> > > USB node
> > > in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .
> > 
> > Hi Marek,
> > 
> > Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2,
> > then usb
> > works,
> > 
> > => usb start
> > starting USB...
> > USB0: Core Release: 2.93a
> > scanning bus 0 for devices... 2 USB Device(s) found
> > => usb tree
> > USB device tree:
> > 1 Hub (480 Mb/s, 0mA)
> > 
> > > U-Boot Root Hub
> > 
> > +-2 Mass Storage (480 Mb/s, 98mA)
> > Generic USB Storage 0272
> 
> Cool, thanks! Patch please ;-)

Nice, guess Altera email is very slow

Thanks
Chin Liang
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Marek Vasut]

On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
> On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > Updated QSPI clock.
> > 
> > Signed-off-by: shengjiangwu 
> > Cc: Chin Liang See 
> > Cc: Dinh Nguyen 
> > Cc: Dinh Nguyen 
> > Cc: Pavel Machek 
> > Cc: Marek Vasut 
> > Cc: Stefan Roese 
> 
> Applied, thanks.
> 
> I will push your patches to [1] in a few hours, can you try and see if the
> CV SOCDK works fine for you? Thanks
> 
> [1] http://git.denx.de/?p=u-boot/u-boot-
> socfpga.git;a=shortlog;h=refs/heads/master

Pushed. Please let me know how SoCDK works for you now and if there are still
some problems.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Chin Liang See]

On Tue, 2015-12-22 at 17:18 +0800, shengjiangwu wrote:
> Updated pinmux group MIXED1IO[15-20] for QSPI.
> Updated QSPI clock.
> 
> Signed-off-by: shengjiangwu 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Dinh Nguyen 
> Cc: Pavel Machek 
> Cc: Marek Vasut 
> Cc: Stefan Roese 
> ---
>  board/altera/cyclone5-socdk/qts/pinmux_config.h |   12 ++--
>  board/altera/cyclone5-socdk/qts/pll_config.h|2 +-
>  2 files changed, 7 insertions(+), 7 deletions(-)
> 


Acked-by: Chin Liang See 

Thanks
Chin Liang
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[U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[shengjiangwu]

Updated pinmux group MIXED1IO[15-20] for QSPI.
Updated QSPI clock.

Signed-off-by: shengjiangwu 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Marek Vasut 
Cc: Stefan Roese 
---
 board/altera/cyclone5-socdk/qts/pinmux_config.h |   12 ++--
 board/altera/cyclone5-socdk/qts/pll_config.h|2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h 
b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index 442b1e0..06783dc 100644
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = {
2, /* MIXED1IO12 */
2, /* MIXED1IO13 */
0, /* MIXED1IO14 */
-   1, /* MIXED1IO15 */
-   1, /* MIXED1IO16 */
-   1, /* MIXED1IO17 */
-   1, /* MIXED1IO18 */
-   0, /* MIXED1IO19 */
-   0, /* MIXED1IO20 */
+   3, /* MIXED1IO15 */
+   3, /* MIXED1IO16 */
+   3, /* MIXED1IO17 */
+   3, /* MIXED1IO18 */
+   3, /* MIXED1IO19 */
+   3, /* MIXED1IO20 */
0, /* MIXED1IO21 */
0, /* MIXED2IO0 */
0, /* MIXED2IO1 */
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h 
b/board/altera/cyclone5-socdk/qts/pll_config.h
index 9e336e3..4abd2e0 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -14,7 +14,7 @@
 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-- 
1.7.9.5

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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[ShengjiangWu]

> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de] 
> Sent: Wednesday, December 23, 2015 9:25 AM
> To: 圣江 吴
> Cc: u-boot@lists.denx.de; cl...@altera.com; dingu...@opensource.altera.com; 
> dinh.li...@gmail.com; pa...@denx.de; s...@denx.de
> Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
> 
> On Wednesday, December 23, 2015 at 02:22:49 AM, 圣江 吴 wrote:
> > On Dec 22, 2015, at 12:33 PM, Marek Vasut  wrote:
> > 
> > On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
> > 
> > On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > > Updated QSPI clock.
> > > 
> > > Signed-off-by: shengjiangwu 
> > > Cc: Chin Liang See 
> > > Cc: Dinh Nguyen 
> > > Cc: Dinh Nguyen 
> > > Cc: Pavel Machek 
> > > Cc: Marek Vasut 
> > > Cc: Stefan Roese 
> > 
> > Applied, thanks.
> > 
> > I will push your patches to [1] in a few hours, can you try and see if 
> > the CV SOCDK works fine for you? Thanks
> > 
> > [1] http://git.denx.de/?p=u-boot/u-boot-
> > socfpga.git;a=shortlog;h=refs/heads/master
> > 
> > Pushed. Please let me know how SoCDK works for you now and if there 
> > are still some problems.
> > 
> > 
> > Best regards,
> > Marek Vasut
> > 
> > 
> > Hi Marek,
> > 
> > Thank you for your help, I tested the master branch, emac1 and QSPI 
> > works. Below is log.
> 
> Good! so we're happy ? Can you give USB a spin too? I think it might have 
> some issues and I don't have the necessary cable here.
> 
> [...]
> 
> Best regards,
> Marek Vasut

Hi Marek,

Yes, emac1 and qspi are working now. I'm afraid USB is not working,

=> usb reset
resetting USB...
USB0:   Core Release: 2.93a
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
scanning bus 0 for devices... 1 USB Device(s) found
=> usb tree
USB device tree:
  1  Hub (480 Mb/s, 0mA)
  U-Boot Root Hub

=>

Best Regards,
ShengjiangWu

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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[圣江 吴]

From: Marek Vasut
Date: 2015-12-23 10:07
To: ShengjiangWu
CC: u-boot; clsee; dinguyen; dinh.linux; pavel; sr
Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
On Wednesday, December 23, 2015 at 03:02:10 AM, ShengjiangWu wrote:
> > -Original Message-
> > From: Marek Vasut [mailto:ma...@denx.de]
> > Sent: Wednesday, December 23, 2015 9:25 AM
> > To: 圣江 吴
> > Cc: u-boot@lists.denx.de; cl...@altera.com;
> > dingu...@opensource.altera.com; dinh.li...@gmail.com; pa...@denx.de;
> > s...@denx.de Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on
> > socdk board
> >
> > On Wednesday, December 23, 2015 at 02:22:49 AM, 圣江 吴 wrote:
> > > On Dec 22, 2015, at 12:33 PM, Marek Vasut  wrote:
> > >
> > > On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
> > >
> > > On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > > > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > > > Updated QSPI clock.
> > > >
> > > > Signed-off-by: shengjiangwu 
> > > > Cc: Chin Liang See 
> > > > Cc: Dinh Nguyen 
> > > > Cc: Dinh Nguyen 
> > > > Cc: Pavel Machek 
> > > > Cc: Marek Vasut 
> > > > Cc: Stefan Roese 
> > >
> > > Applied, thanks.
> > >
> > > I will push your patches to [1] in a few hours, can you try and see if
> > > the CV SOCDK works fine for you? Thanks
> > >
> > > [1] http://git.denx.de/?p=u-boot/u-boot-
> > > socfpga.git;a=shortlog;h=refs/heads/master
> > >
> > > Pushed. Please let me know how SoCDK works for you now and if there
> > > are still some problems.
> > >
> > >
> > > Best regards,
> > > Marek Vasut
> > >
> > >
> > > Hi Marek,
> > >
> > > Thank you for your help, I tested the master branch, emac1 and QSPI
> > > works. Below is log.
> >
> > Good! so we're happy ? Can you give USB a spin too? I think it might have
> > some issues and I don't have the necessary cable here.
> >
> > [...]
> >
> > Best regards,
> > Marek Vasut
>
> Hi Marek,
>
> Yes, emac1 and qspi are working now. I'm afraid USB is not working,
>
> => usb reset
> resetting USB...
> USB0: Core Release: 2.93a
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> scanning bus 0 for devices... 1 USB Device(s) found
> => usb tree
> USB device tree:
> 1 Hub (480 Mb/s, 0mA)
> U-Boot Root Hub

Hm, darn. Can you or Chin check it ? It's either pinmux or wrong USB node
in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .


Hi Marek,

Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2, then usb works,

=> usb start
starting USB...
USB0: Core Release: 2.93a
scanning bus 0 for devices... 2 USB Device(s) found
=> usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)
| U-Boot Root Hub
|
+-2 Mass Storage (480 Mb/s, 98mA)
Generic USB Storage 0272

=>

Best Regards,
ShengjiangWu
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[圣江 吴]

On Dec 22, 2015, at 12:33 PM, Marek Vasut  wrote:

On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:

Updated pinmux group MIXED1IO[15-20] for QSPI.
Updated QSPI clock.

Signed-off-by: shengjiangwu 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Marek Vasut 
Cc: Stefan Roese 


Applied, thanks.

I will push your patches to [1] in a few hours, can you try and see if the
CV SOCDK works fine for you? Thanks

[1] http://git.denx.de/?p=u-boot/u-boot-
socfpga.git;a=shortlog;h=refs/heads/master

Pushed. Please let me know how SoCDK works for you now and if there are still
some problems.


Best regards,
Marek Vasut


Hi Marek,

Thank you for your help, I tested the master branch, emac1 and QSPI works. 
Below is log.

Best Regards,
ShengjiangWu

=> reset
resetting ...

U-Boot SPL 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
drivers/ddr/altera/sequencer.c: Calibration complete
Trying to boot from MMC


U-Boot 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52 +0800)

CPU: Altera SoCFPGA Platform
FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT: SD/MMC External Transceiver (1.8V)
Watchdog enabled
I2C: ready
DRAM: 1 GiB
MMC: dwmmc0@ff704000: 0
*** Warning - bad CRC, using default environment

In: serial
Out: serial
Err: serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net:
Error: ethernet@ff702000 address not set.
No ethernet found.
Hit any key to stop autoboot: 0
=> env default -a
## Resetting to default environment
=> setenv netmask 255.255.254.0
=> setenv gatewayip 128.224.98.1
=> setenv ipaddr 128.224.98.85
=> setenv serverip 128.224.99.137
=> setenv ethaddr 00:04:9f:13:57:b4
=> saveenv
Saving Environment to MMC...
Writing to MMC(0)... done
=> reset
resetting ...

U-Boot SPL 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
drivers/ddr/altera/sequencer.c: Calibration complete
Trying to boot from MMC


U-Boot 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52 +0800)

CPU: Altera SoCFPGA Platform
FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT: SD/MMC External Transceiver (1.8V)
Watchdog enabled
I2C: ready
DRAM: 1 GiB
MMC: dwmmc0@ff704000: 0
In: serial
Out: serial
Err: serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net: eth0: ethernet@ff702000
Hit any key to stop autoboot: 0
=> tftp 0x800 /tftpboot/altera/uVxWorks
Speed: 100, full duplex
Using ethernet@ff702000 device
TFTP from server 128.224.99.137; our IP address is 128.224.98.85
Filename '/tftpboot/altera/uVxWorks'.
Load address: 0x800
Loading: #
#
#
#
#
#

3.3 MiB/s
done
Bytes transferred = 6418496 (61f040 hex)
=> sf probe
SF: Detected N25Q1024 with page size 256 Bytes, erase size 64 KiB, total 128 MiB
=> sf read 0x700 0 0x6
device 0 offset 0x0, size 0x6
SF: 393216 bytes @ 0x0 Read: OK
=> md 0x700
0700: ea1a e59ff014 e59ff014 e59ff014 
0710: e59ff014 e59ff014 e59ff014 e59ff014 
0720: 0020 0024 0028 002c ...$...(...,...
0730: 0030 0100 0038 12345678 0...8...xV4.
0740: 31305341 2e16 0139 ea07 AS01..9.
0750: 0140 b854 b854 b900 @...T...T...
0760: b854 0badc0de 0badc0de 0badc0de T...
0770: eb40 e10f e3c0001f e38000d3 @...
0780: e129f000 ee110f10 e3c00a02 ee010f10 ..).
0790: e59f00a8 ee0c0f10 eb08 eb15 
07a0: eb000690 ee070f15 ee070f9a ee070f95 
07b0: e59f0088 ee0c0f10 e12fff1e e12fff1e ../.../.
07c0: e3a0 ee080f17 ee070f15 ee070fd5 
07d0: ee070f9a ee070f95 ee110f10 e3c00a02 
07e0: e3c7 e382 e3800b02 e3800a01 
07f0: ee010f10 e1a0f00e ea18 e320f000 .. .
=>
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Marek Vasut]

On Monday, December 21, 2015 at 11:41:24 AM, Pavel Machek wrote:
> On Mon 2015-12-21 11:12:29, Marek Vasut wrote:
> > On Monday, December 21, 2015 at 10:37:23 AM, Pavel Machek wrote:
> > > On Mon 2015-12-21 07:33:34, 圣江 吴 wrote:
> > > > Hi Marek Vasut,
> > > > 
> > > > 
> > > > On Dec 18, 2015, at 04:50 AM, Marek Vasut  wrote:
> > > > 
> > > > On Friday, December 18, 2015 at 08:57:22 AM, 圣江 吴 wrote:
> > > > Hi Chin,
> > > > 
> > > > The PLL settings are copied from previous version
> > > > http://git.rocketboards.org/u-boot-socfpga.git,
> > > > 
> > > > This stuff should be generated by quartus, so why are you copying it
> > > > from some random version of u-boot somewhere ?
> > > > 
> > > > Thank you for your comment, if this configuration
> > > > is automatically generated by Quartus without manually modification,
> > > > then I would like to withdraw this patch.
> > > 
> > > No, please don't. socdk should work out of the box.
> > 
> > SoCDK works out of the box last time I checked (2016.01rc1), did you test
> > it recently and do you observe problems ?
> 
> Did you test QSPI? Because that is what subject claims does not work.

I'd have to retest that one, I only recall it booted and the basic functionality
was OK. Feel free to test QSPI again, that'd be actually helpful.

> > > I should not need
> > > quartus to build a working u-boot spl for the board.
> > 
> > You DO need quartus to generate the header files (that go into
> > board/nnn/qts) to build working U-Boot SPL for any board. I fail to
> > understand your comment, sorry.
> 
> Ok, lets talk about this personally or over phone.

Please stick to the ML.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[圣江 吴]

Hi Marek Vasut,


On Dec 18, 2015, at 04:50 AM, Marek Vasut  wrote:

On Friday, December 18, 2015 at 08:57:22 AM, 圣江 吴 wrote:
Hi Chin,

The PLL settings are copied from previous version
http://git.rocketboards.org/u-boot-socfpga.git,

This stuff should be generated by quartus, so why are you copying it from
some random version of u-boot somewhere ?

Thank you for your comment, if this configuration is automatically generated by 
Quartus without manually modification, then I would like to withdraw this patch.

Best Regards,
Shengjiang Wu
 

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Marek Vasut]

On Monday, December 21, 2015 at 10:37:23 AM, Pavel Machek wrote:
> On Mon 2015-12-21 07:33:34, 圣江 吴 wrote:
> > Hi Marek Vasut,
> > 
> > 
> > On Dec 18, 2015, at 04:50 AM, Marek Vasut  wrote:
> > 
> > On Friday, December 18, 2015 at 08:57:22 AM, 圣江 吴 wrote:
> > Hi Chin,
> > 
> > The PLL settings are copied from previous version
> > http://git.rocketboards.org/u-boot-socfpga.git,
> > 
> > This stuff should be generated by quartus, so why are you copying it from
> > some random version of u-boot somewhere ?
> > 
> > Thank you for your comment, if this configuration
> > is automatically generated by Quartus without manually modification,
> > then I would like to withdraw this patch.
> 
> No, please don't. socdk should work out of the box.

SoCDK works out of the box last time I checked (2016.01rc1), did you test it 
recently and do you observe problems ?

> I should not need
> quartus to build a working u-boot spl for the board.

You DO need quartus to generate the header files (that go into board/nnn/qts)
to build working U-Boot SPL for any board. I fail to understand your comment,
sorry.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Pavel Machek]

On Mon 2015-12-21 11:12:29, Marek Vasut wrote:
> On Monday, December 21, 2015 at 10:37:23 AM, Pavel Machek wrote:
> > On Mon 2015-12-21 07:33:34, 圣江 吴 wrote:
> > > Hi Marek Vasut,
> > > 
> > > 
> > > On Dec 18, 2015, at 04:50 AM, Marek Vasut  wrote:
> > > 
> > > On Friday, December 18, 2015 at 08:57:22 AM, 圣江 吴 wrote:
> > > Hi Chin,
> > > 
> > > The PLL settings are copied from previous version
> > > http://git.rocketboards.org/u-boot-socfpga.git,
> > > 
> > > This stuff should be generated by quartus, so why are you copying it from
> > > some random version of u-boot somewhere ?
> > > 
> > > Thank you for your comment, if this configuration
> > > is automatically generated by Quartus without manually modification,
> > > then I would like to withdraw this patch.
> > 
> > No, please don't. socdk should work out of the box.
> 
> SoCDK works out of the box last time I checked (2016.01rc1), did you test it 
> recently and do you observe problems ?

Did you test QSPI? Because that is what subject claims does not work.

> > I should not need
> > quartus to build a working u-boot spl for the board.
> 
> You DO need quartus to generate the header files (that go into board/nnn/qts)
> to build working U-Boot SPL for any board. I fail to understand your comment,
> sorry.

Ok, lets talk about this personally or over phone.

Best regards,
Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) 
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Pavel Machek]

On Mon 2015-12-21 07:33:34, 圣江 吴 wrote:
> Hi Marek Vasut,
> 
> 
> On Dec 18, 2015, at 04:50 AM, Marek Vasut  wrote:
> 
> On Friday, December 18, 2015 at 08:57:22 AM, 圣江 吴 wrote:
> Hi Chin,
> 
> The PLL settings are copied from previous version
> http://git.rocketboards.org/u-boot-socfpga.git,
> 
> This stuff should be generated by quartus, so why are you copying it from
> some random version of u-boot somewhere ?

> Thank you for your comment, if this configuration is automatically generated 
> by Quartus without manually modification, then I would like to withdraw this 
> patch.
> 

No, please don't. socdk should work out of the box. I should not need
quartus to build a working u-boot spl for the board.
Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) 
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Chin Liang See]

On Mon, 2015-12-21 at 10:37 +0100, Pavel Machek wrote:
> On Mon 2015-12-21 07:33:34, 圣江 吴 wrote:
> > Hi Marek Vasut,
> > 
> > 
> > On Dec 18, 2015, at 04:50 AM, Marek Vasut  wrote:
> > 
> > On Friday, December 18, 2015 at 08:57:22 AM, 圣江 吴 wrote:
> > Hi Chin,
> > 
> > The PLL settings are copied from previous version
> > http://git.rocketboards.org/u-boot-socfpga.git,
> > 
> > This stuff should be generated by quartus, so why are you copying
> > it from
> > some random version of u-boot somewhere ?
> 
> > Thank you for your comment, if this configuration is automatically
> >  generated by Quartus without manually modification, then I would
> > like to withdraw this patch.
> > 
> 
> No, please don't. socdk should work out of the box. I should not need
> quartus to build a working u-boot spl for the board.
> 

Yah, let's upstream this. I believe the advise here is that we use the
handoff file from quartus as a golden reference.

Thanks
Chin Liang

>   
> Pavel
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Marek Vasut]

On Monday, December 21, 2015 at 10:56:14 AM, Chin Liang See wrote:
> On Mon, 2015-12-21 at 10:37 +0100, Pavel Machek wrote:
> > On Mon 2015-12-21 07:33:34, 圣江 吴 wrote:
> > > Hi Marek Vasut,
> > > 
> > > 
> > > On Dec 18, 2015, at 04:50 AM, Marek Vasut  wrote:
> > > 
> > > On Friday, December 18, 2015 at 08:57:22 AM, 圣江 吴 wrote:
> > > Hi Chin,
> > > 
> > > The PLL settings are copied from previous version
> > > http://git.rocketboards.org/u-boot-socfpga.git,
> > > 
> > > This stuff should be generated by quartus, so why are you copying
> > > it from
> > > some random version of u-boot somewhere ?
> > > 
> > > Thank you for your comment, if this configuration is automatically
> > > 
> > >  generated by Quartus without manually modification, then I would
> > > 
> > > like to withdraw this patch.
> > 
> > No, please don't. socdk should work out of the box. I should not need
> > quartus to build a working u-boot spl for the board.
> 
> Yah, let's upstream this. I believe the advise here is that we use the
> handoff file from quartus as a golden reference.

The ones in mainline are from GHRD I believe.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[圣江 吴]

Hi Chin,

The PLL settings are copied from previous version 
http://git.rocketboards.org/u-boot-socfpga.git, 

On Dec 17, 2015, at 11:45 PM, Chin Liang See  wrote:

Hi Shengjiang,

On Fri, 2015-12-18 at 15:21 +0800, shengjiangwu wrote:
Updated pinmux group MIXED1IO[15-20] for QSPI.
Updated QSPI clock.

Signed-off-by: shengjiangwu 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Marek Vasut 
Cc: Stefan Roese 
---
board/altera/cyclone5-socdk/qts/pinmux_config.h | 12 ++--
board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++--
2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h
b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index 442b1e0..06783dc 100644
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = {
       2, /* MIXED1IO12 */
       2, /* MIXED1IO13 */
       0, /* MIXED1IO14 */
-        1, /* MIXED1IO15 */
-        1, /* MIXED1IO16 */
-        1, /* MIXED1IO17 */
-        1, /* MIXED1IO18 */
-        0, /* MIXED1IO19 */
-        0, /* MIXED1IO20 */
+        3, /* MIXED1IO15 */
+        3, /* MIXED1IO16 */
+        3, /* MIXED1IO17 */
+        3, /* MIXED1IO18 */
+        3, /* MIXED1IO19 */
+        3, /* MIXED1IO20 */
       0, /* MIXED1IO21 */
       0, /* MIXED2IO0 */
 0, /* MIXED2IO1 */
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h
b/board/altera/cyclone5-socdk/qts/pll_config.h
index 42905f4..eccc705 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -14,7 +14,7 @@
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
@@ -32,7 +32,7 @@
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1

Let's not change this as we are using mainpll for QSPI clock. Besides
that, the QSPI perpll will yield 500MHz which exceed the 400MHz max
clock.

Thanks
Chin Liang

OK, I will restore CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT as 511

Thanks ShengjiangWu
 


#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
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[U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[shengjiangwu]

Updated pinmux group MIXED1IO[15-20] for QSPI.
Updated QSPI clock.

Signed-off-by: shengjiangwu 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Marek Vasut 
Cc: Stefan Roese 
---
 board/altera/cyclone5-socdk/qts/pinmux_config.h |   12 ++--
 board/altera/cyclone5-socdk/qts/pll_config.h|4 ++--
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h 
b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index 442b1e0..06783dc 100644
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = {
2, /* MIXED1IO12 */
2, /* MIXED1IO13 */
0, /* MIXED1IO14 */
-   1, /* MIXED1IO15 */
-   1, /* MIXED1IO16 */
-   1, /* MIXED1IO17 */
-   1, /* MIXED1IO18 */
-   0, /* MIXED1IO19 */
-   0, /* MIXED1IO20 */
+   3, /* MIXED1IO15 */
+   3, /* MIXED1IO16 */
+   3, /* MIXED1IO17 */
+   3, /* MIXED1IO18 */
+   3, /* MIXED1IO19 */
+   3, /* MIXED1IO20 */
0, /* MIXED1IO21 */
0, /* MIXED2IO0 */
0, /* MIXED2IO1 */
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h 
b/board/altera/cyclone5-socdk/qts/pll_config.h
index 42905f4..eccc705 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -14,7 +14,7 @@
 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
@@ -32,7 +32,7 @@
 #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
 #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1
 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
 #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-- 
1.7.9.5

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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Marek Vasut]

On Friday, December 18, 2015 at 08:57:22 AM, 圣江 吴 wrote:
> Hi Chin,
> 
> The PLL settings are copied from previous version
> http://git.rocketboards.org/u-boot-socfpga.git, 

This stuff should be generated by quartus, so why are you copying it from
some random version of u-boot somewhere ?

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Chin Liang See]

Hi Shengjiang,

On Fri, 2015-12-18 at 15:21 +0800, shengjiangwu wrote:
> Updated pinmux group MIXED1IO[15-20] for QSPI.
> Updated QSPI clock.
> 
> Signed-off-by: shengjiangwu 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Dinh Nguyen 
> Cc: Pavel Machek 
> Cc: Marek Vasut 
> Cc: Stefan Roese 
> ---
>  board/altera/cyclone5-socdk/qts/pinmux_config.h |   12 ++--
>  board/altera/cyclone5-socdk/qts/pll_config.h|4 ++--
>  2 files changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> index 442b1e0..06783dc 100644
> --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> @@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = {
>   2, /* MIXED1IO12 */
>   2, /* MIXED1IO13 */
>   0, /* MIXED1IO14 */
> - 1, /* MIXED1IO15 */
> - 1, /* MIXED1IO16 */
> - 1, /* MIXED1IO17 */
> - 1, /* MIXED1IO18 */
> - 0, /* MIXED1IO19 */
> - 0, /* MIXED1IO20 */
> + 3, /* MIXED1IO15 */
> + 3, /* MIXED1IO16 */
> + 3, /* MIXED1IO17 */
> + 3, /* MIXED1IO18 */
> + 3, /* MIXED1IO19 */
> + 3, /* MIXED1IO20 */
>   0, /* MIXED1IO21 */
>   0, /* MIXED2IO0 */
>   0, /* MIXED2IO1 */
> diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h
> b/board/altera/cyclone5-socdk/qts/pll_config.h
> index 42905f4..eccc705 100644
> --- a/board/altera/cyclone5-socdk/qts/pll_config.h
> +++ b/board/altera/cyclone5-socdk/qts/pll_config.h
> @@ -14,7 +14,7 @@
>  #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
>  #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
>  #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
> -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
> +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
>  #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
>  #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
>  #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
> @@ -32,7 +32,7 @@
>  #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
>  #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
>  #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
> -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
> +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1

Let's not change this as we are using mainpll for QSPI clock. Besides
that, the QSPI perpll will yield 500MHz which exceed the 400MHz max
clock.

Thanks
Chin Liang


>  #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
>  #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
>  #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
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