Re: [U-Boot] [PATCH] armv8: fsl-lsch2: enable snoopable usb read and write

[Stuart Yoder]

> -Original Message-
> From: Changming Huang [mailto:jerry.hu...@nxp.com]
> Sent: Thursday, December 15, 2016 1:45 AM
> To: york sun ; u-boot@lists.denx.de; Stuart Yoder 
> 
> Cc: Jerry Huang 
> Subject: [PATCH] armv8: fsl-lsch2: enable snoopable usb read and write
> 
> By default the USB IP on the ls1012a/ls1043a/ls1046a SoCs does not
> generat coherent/snoopable transactions. Here enable it in the
> SCFG_SNPCNFGCR register.
> In addition, the dma-coherent property must be set in USB DTS nodes.
> 
> Signed-off-by: Changming Huang 
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c|   13 -
>  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |6 ++
>  2 files changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> index 2f54625..74eb8a1 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -340,6 +340,7 @@ void fsl_lsch2_early_init_f(void)
>  {
>   struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
>   struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
> + u32 snp_usb;
> 
>  #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
>   enable_layerscape_ns_access();
> @@ -352,11 +353,21 @@ void fsl_lsch2_early_init_f(void)
>  #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
>   out_be32(>qspi_cfg, SCFG_QSPI_CLKSEL);
>  #endif
> +
> + snp_usb = SCFG_SNPCNFGCR_USB1RDSNP | SCFG_SNPCNFGCR_USB1WRSNP;
> +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
> + snp_usb |= SCFG_SNPCNFGCR_USB2WRSNP |
> + SCFG_SNPCNFGCR_USB2RDSNP |
> + SCFG_SNPCNFGCR_USB3WRSNP |
> + SCFG_SNPCNFGCR_USB3RDSNP;
> +#endif
> +
>   /* Make SEC reads and writes snoopable */

Fix the above comment...it is not only about SEC anymore.

Stuart
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[U-Boot] [PATCH] armv8: fsl-lsch2: enable snoopable usb read and write

[Changming Huang]

By default the USB IP on the ls1012a/ls1043a/ls1046a SoCs does not
generat coherent/snoopable transactions. Here enable it in the
SCFG_SNPCNFGCR register.
In addition, the dma-coherent property must be set in USB DTS nodes.

Signed-off-by: Changming Huang 
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c|   13 -
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |6 ++
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 2f54625..74eb8a1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -340,6 +340,7 @@ void fsl_lsch2_early_init_f(void)
 {
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+   u32 snp_usb;
 
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
@@ -352,11 +353,21 @@ void fsl_lsch2_early_init_f(void)
 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
out_be32(>qspi_cfg, SCFG_QSPI_CLKSEL);
 #endif
+
+   snp_usb = SCFG_SNPCNFGCR_USB1RDSNP | SCFG_SNPCNFGCR_USB1WRSNP;
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+   snp_usb |= SCFG_SNPCNFGCR_USB2WRSNP |
+   SCFG_SNPCNFGCR_USB2RDSNP |
+   SCFG_SNPCNFGCR_USB3WRSNP |
+   SCFG_SNPCNFGCR_USB3RDSNP;
+#endif
+
/* Make SEC reads and writes snoopable */
setbits_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
 SCFG_SNPCNFGCR_SECWRSNP |
 SCFG_SNPCNFGCR_SATARDSNP |
-SCFG_SNPCNFGCR_SATAWRSNP);
+SCFG_SNPCNFGCR_SATAWRSNP |
+snp_usb);
 
/*
 * Enable snoop requests and DVM message requests for
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index b3cfd89..b82db03 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -340,6 +340,12 @@ struct ccsr_gur {
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
 #define SCFG_SNPCNFGCR_SATARDSNP   0x0080
 #define SCFG_SNPCNFGCR_SATAWRSNP   0x0040
+#define SCFG_SNPCNFGCR_USB1RDSNP   0x0020
+#define SCFG_SNPCNFGCR_USB1WRSNP   0x0010
+#define SCFG_SNPCNFGCR_USB2WRSNP   0x0001
+#define SCFG_SNPCNFGCR_USB2RDSNP   0x8000
+#define SCFG_SNPCNFGCR_USB3WRSNP   0x4000
+#define SCFG_SNPCNFGCR_USB3RDSNP   0x2000
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
1.7.9.5

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