Re: [U-Boot] [PATCH] armv8: fsl-lsch3: enable snoopable sata read and write

2017-01-19 Thread york sun 
On 12/01/2016 01:20 AM, yuantian.t...@nxp.com wrote:
> From: Tang Yuantian 
>
> By default the SATA IP on the ls208Xa SoCs does not generating
> coherent/snoopable transactions.  This patch enable it in the
> sata axicc register.
>
> Signed-off-by: Tang Yuantian 
> ---

Applied to fsl-qoriq master, awaiting upstream. Thanks.

York

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Re: [U-Boot] [PATCH] armv8: fsl-lsch3: enable snoopable sata read and write

2017-01-05 Thread york sun 
On 01/04/2017 08:47 PM, Y.T. Tang wrote:
> Hi York,
>
> For chasis2 platforms, like ls1043a and ls1046a, similar patch has been 
> merged already.
>

Ah! I see them in a wider range. You have them under #elif 
defined(CONFIG_FSL_LSCH2). It isn't visible in this patch.

York
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Re: [U-Boot] [PATCH] armv8: fsl-lsch3: enable snoopable sata read and write

2017-01-04 Thread Y.T. Tang 
Hi York,

For chasis2 platforms, like ls1043a and ls1046a, similar patch has been merged 
already.

Patch information:

commit 4de6ce1594fcff6fa9e626d094fa922f4889e167
Author: Tang Yuantian 
Date:   Mon Aug 8 15:07:20 2016

armv8: fsl-lsch2: enable snoopable sata read and write

By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions.  This patch enable
it in the SCFG_SNPCNFGCR register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA
controller nodes.

Signed-off-by: Tang Yuantian 
[York Sun: Reformatted commit message]
Reviewed-by: York Sun 

Regards,
Yuantian

> -Original Message-
> From: york sun
> Sent: Thursday, January 05, 2017 3:38 AM
> To: Y.T. Tang ; albert.u.b...@aribaud.net
> Cc: u-boot@lists.denx.de
> Subject: Re: [PATCH] armv8: fsl-lsch3: enable snoopable sata read and write
> 
> On 12/01/2016 01:20 AM, yuantian.t...@nxp.com wrote:
> > From: Tang Yuantian 
> >
> > By default the SATA IP on the ls208Xa SoCs does not generating
> > coherent/snoopable transactions.  This patch enable it in the sata
> > axicc register.
> 
> How about ls1043a, ls1046a? You didn't check SVR.
> 
> York

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Re: [U-Boot] [PATCH] armv8: fsl-lsch3: enable snoopable sata read and write

2017-01-04 Thread york sun 
On 12/01/2016 01:20 AM, yuantian.t...@nxp.com wrote:
> From: Tang Yuantian 
>
> By default the SATA IP on the ls208Xa SoCs does not generating
> coherent/snoopable transactions.  This patch enable it in the
> sata axicc register.

How about ls1043a, ls1046a? You didn't check SVR.

York

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[U-Boot] [PATCH] armv8: fsl-lsch3: enable snoopable sata read and write

2016-12-01 Thread yuantian.tang 
From: Tang Yuantian 

By default the SATA IP on the ls208Xa SoCs does not generating
coherent/snoopable transactions.  This patch enable it in the
sata axicc register.

Signed-off-by: Tang Yuantian 
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6c42387..80fdca5 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -213,10 +213,12 @@ int sata_init(void)
ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
+   out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
+   out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
ahci_init((void __iomem *)CONFIG_SYS_SATA1);
scsi_scan(0);
-- 
2.1.0.27.g96db324

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