Re: [U-Boot] [PATCH] board: tbs2910: Gate clock when switching async clock muxes
On 23/01/2015 19:03, Soeren Moch wrote: According to the i.MX6Q Reference Manual, clocks must be gated when switching input clocks of async clock muxes. So use clock gates. Avoid ldb_di0_ipu clock, because there is no clock gate for this signal. There have never been any complaints about problems with the old code, but the new approach is in line with the recommendations in the manual. Signed-off-by: Soeren Moch sm...@web.de -- Cc: Stefano Babic sba...@denx.de --- Applied to u-boot-imx, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] board: tbs2910: Gate clock when switching async clock muxes
Hi Soeren, On 19/02/2015 00:28, Soeren Moch wrote: Hi Stefano, On 19.02.2015 00:08, Stefano Babic wrote: Hi Soeren, On 18/02/2015 16:43, Soeren Moch wrote: According to the i.MX6Q Reference Manual, clocks must be gated when switching input clocks of async clock muxes. So use clock gates. Avoid ldb_di0_ipu clock, because there is no clock gate for this signal. There have never been any complaints about problems with the old code, but the new approach is in line with the recommendations in the manual. Signed-off-by: Soeren Moch sm...@web.de -- Cc: Stefano Babic sba...@denx.de Stefano, this patch missed several commit cycles now. Do you think it should not be merged? No, but it was not in my list on patchwork - I checked now and the patch was delegated to York. Maybe he is also asking why, because it is strictly i.MX related. I set the patch to myself and I will merge it. Thanks for raising this. Best regards, Stefano Babic Ah, ok. Is there any opportunity to assign a patch in patchwork when sending it? There is no way. However, no problem. Thanks, Soeren Cheers, Stefano -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] board: tbs2910: Gate clock when switching async clock muxes
According to the i.MX6Q Reference Manual, clocks must be gated when switching input clocks of async clock muxes. So use clock gates. Avoid ldb_di0_ipu clock, because there is no clock gate for this signal. There have never been any complaints about problems with the old code, but the new approach is in line with the recommendations in the manual. Signed-off-by: Soeren Moch sm...@web.de -- Cc: Stefano Babic sba...@denx.de Stefano, this patch missed several commit cycles now. Do you think it should not be merged? Regards, Soeren ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] board: tbs2910: Gate clock when switching async clock muxes
Hi Soeren, On 18/02/2015 16:43, Soeren Moch wrote: According to the i.MX6Q Reference Manual, clocks must be gated when switching input clocks of async clock muxes. So use clock gates. Avoid ldb_di0_ipu clock, because there is no clock gate for this signal. There have never been any complaints about problems with the old code, but the new approach is in line with the recommendations in the manual. Signed-off-by: Soeren Moch sm...@web.de -- Cc: Stefano Babic sba...@denx.de Stefano, this patch missed several commit cycles now. Do you think it should not be merged? No, but it was not in my list on patchwork - I checked now and the patch was delegated to York. Maybe he is also asking why, because it is strictly i.MX related. I set the patch to myself and I will merge it. Thanks for raising this. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] board: tbs2910: Gate clock when switching async clock muxes
Hi Stefano, On 19.02.2015 00:08, Stefano Babic wrote: Hi Soeren, On 18/02/2015 16:43, Soeren Moch wrote: According to the i.MX6Q Reference Manual, clocks must be gated when switching input clocks of async clock muxes. So use clock gates. Avoid ldb_di0_ipu clock, because there is no clock gate for this signal. There have never been any complaints about problems with the old code, but the new approach is in line with the recommendations in the manual. Signed-off-by: Soeren Moch sm...@web.de -- Cc: Stefano Babic sba...@denx.de Stefano, this patch missed several commit cycles now. Do you think it should not be merged? No, but it was not in my list on patchwork - I checked now and the patch was delegated to York. Maybe he is also asking why, because it is strictly i.MX related. I set the patch to myself and I will merge it. Thanks for raising this. Best regards, Stefano Babic Ah, ok. Is there any opportunity to assign a patch in patchwork when sending it? However, no problem. Thanks, Soeren ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] board: tbs2910: Gate clock when switching async clock muxes
According to the i.MX6Q Reference Manual, clocks must be gated when switching input clocks of async clock muxes. So use clock gates. Avoid ldb_di0_ipu clock, because there is no clock gate for this signal. There have never been any complaints about problems with the old code, but the new approach is in line with the recommendations in the manual. Signed-off-by: Soeren Moch sm...@web.de -- Cc: Stefano Babic sba...@denx.de --- board/tbs/tbs2910/tbs2910.c | 28 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c index dfa430e..42b166d 100644 --- a/board/tbs/tbs2910/tbs2910.c +++ b/board/tbs/tbs2910/tbs2910.c @@ -326,21 +326,25 @@ static void setup_display(void) reg = ~BM_ANADIG_PLL_VIDEO_BYPASS; writel(reg, ccm-analog_pll_video); - /* select video pll for ldb_di0_clk */ - reg = readl(ccm-cs2cdr); - reg = ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK); - writel(reg, ccm-cs2cdr); + /* gate ipu1_di0_clk */ + reg = readl(ccm-CCGR3); + reg = ~MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, ccm-CCGR3); - /* select ldb_di0_clk / 7 for ldb_di0_ipu_clk */ - reg = readl(ccm-cscmr2); - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; - writel(reg, ccm-cscmr2); - - /* select ldb_di0_ipu_clk for ipu1_di0_clk - 65MHz pixclock */ + /* select video_pll clock / 7 for ipu1_di0_clk - 65MHz pixclock */ reg = readl(ccm-chsccdr); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 -MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + reg = ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK | +MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK | +MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); + reg |= (2 MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) | + (6 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) | + (0 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); writel(reg, ccm-chsccdr); + + /* enable ipu1_di0_clk */ + reg = readl(ccm-CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, ccm-CCGR3); } #endif /* CONFIG_VIDEO_IPUV3 */ -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
