Re: [U-Boot] [PATCH] davinci: omapl138_lcdk: fix tXSNR DDR2 timing value

[Tom Rini]

On Fri, Jun 02, 2017 at 06:07:12PM +0530, Sekhar Nori wrote:

> As per the datasheet[1] available for DDR2 part on board
> the OMAP-L138 LCDK, the tXSNR (exit self refresh to a
> non-read command) is 137.5 ns. This corresponds to a
> value of 20 to be written to T_XSNR register field of
> OMAP-L138's DDR configuration. The DDR2 is at 150 MHz.
> 
> Fix this. The correct value also appears on the initialization
> scripts (called CCS GEL files) available on TI's wiki pages[2]
> 
> [1] 
> http://www.samsung.com/global/business/semiconductor/file/product/ds_k4t1gxx4qf_rev12-0.pdf
> [2] 
> http://processors.wiki.ti.com/index.php/L138/C6748_Development_Kit_(LCDK)#CCS_XML_.26_GEL_Files
> 
> Signed-off-by: Sekhar Nori 

Reviewed-by: Tom Rini 

-- 
Tom


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[U-Boot] [PATCH] davinci: omapl138_lcdk: fix tXSNR DDR2 timing value

[Sekhar Nori]

As per the datasheet[1] available for DDR2 part on board
the OMAP-L138 LCDK, the tXSNR (exit self refresh to a
non-read command) is 137.5 ns. This corresponds to a
value of 20 to be written to T_XSNR register field of
OMAP-L138's DDR configuration. The DDR2 is at 150 MHz.

Fix this. The correct value also appears on the initialization
scripts (called CCS GEL files) available on TI's wiki pages[2]

[1] 
http://www.samsung.com/global/business/semiconductor/file/product/ds_k4t1gxx4qf_rev12-0.pdf
[2] 
http://processors.wiki.ti.com/index.php/L138/C6748_Development_Kit_(LCDK)#CCS_XML_.26_GEL_Files

Signed-off-by: Sekhar Nori 
---
 include/configs/omapl138_lcdk.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 9db4eeb54edf..88cdf08b1979 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -110,7 +110,7 @@
(7 << DV_DDR_SDTMR2_RASMAX_SHIFT)   | \
(2 << DV_DDR_SDTMR2_XP_SHIFT)   | \
(0 << DV_DDR_SDTMR2_ODT_SHIFT)  | \
-   (10 << DV_DDR_SDTMR2_XSNR_SHIFT)| \
+   (20 << DV_DDR_SDTMR2_XSNR_SHIFT)| \
(199 << DV_DDR_SDTMR2_XSRD_SHIFT)   | \
(1 << DV_DDR_SDTMR2_RTP_SHIFT)  | \
(2 << DV_DDR_SDTMR2_CKE_SHIFT))
-- 
2.9.0

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