Re: [U-Boot] [PATCH] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM

2019-04-10 Thread Martyn Welch 
On Wed, 2019-04-10 at 15:23 +0200, Parthiban Nallathambi wrote:
> Hello Wadim,
> 
> Thanks for sharing the details.
> 
> On 4/10/19 10:35 AM, Wadim Egorov wrote:
> > Martyn,
> > 
> > On 09.04.19 12:46, Martyn Welch wrote:
> > > On Tue, 2019-04-09 at 11:30 +0200, Parthiban Nallathambi wrote:
> > > > Hello Martyn,
> > > > 
> > > > On 4/9/19 10:49 AM, Martyn Welch wrote:
> > > > > On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote:
> > > > > > Hello Martyn,
> > > > > > 
> > > > > > On 4/8/19 7:45 PM, Martyn Welch wrote:
> > > > > > > On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi
> > > > > > > wrote:
> > > > > > > > diff --git a/board/phytec/pcl063/spl.c
> > > > > > > > b/board/phytec/pcl063/spl.c
> > > > > > > > index b93cd493f2..73a774645d 100644
> > > > > > > > --- a/board/phytec/pcl063/spl.c
> > > > > > > > +++ b/board/phytec/pcl063/spl.c
> > > > > > > > @@ -13,6 +13,7 @@
> > > > > > > >#include 
> > > > > > > >#include 
> > > > > > > >#include 
> > > > > > > > +#include 
> > > > > > > >#include 
> > > > > > > >
> > > > > > > >/* Configuration for Micron MT41K256M16TW-107 IT:P,
> > > > > > > > 32M x
> > > > > > > > 16 x 8
> > > > > > > > ->
> > > > > > > > 256MiB */
> > > > > > > > @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const
> > > > > > > > usdhc1_pads[] =
> > > > > > > > {
> > > > > > > > MX6_PAD_UART1_RTS_B__USDHC1_CD_B |
> > > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > >};
> > > > > > > >
> > > > > > > > +#ifndef CONFIG_NAND_MXS
> > > > > > > > +static iomux_v3_cfg_t const usdhc2_pads[] = {
> > > > > > > > +   MX6_PAD_NAND_RE_B__USDHC2_CLK|
> > > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > > +   MX6_PAD_NAND_WE_B__USDHC2_CMD|
> > > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > > +   MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
> > > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > > +   MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
> > > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > > +   MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
> > > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > > +   MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
> > > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > > +   MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
> > > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > > +   MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
> > > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > > +   MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
> > > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > > +   MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
> > > > > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > > > > +};
> > > > > > > > +#endif
> > > > > > > > +
> > > > > > > Umm, these pins are already used a few lines up for the
> > > > > > > NAND,
> > > > > > > via
> > > > > > > gpmi:
> > > > > > I understand. But pcl063 can't co-exit with NAND and eMMC
> > > > > > together. I
> > > > > > comes
> > > > > > either with eMMC or NAND.
> > > > > Opps, sorry, just realised that I added this comment in the
> > > > > wrong
> > > > > place. This is in relation to the following being added to
> > > > > pcl063-common.dtsi:
> > > > > 
> > > > > +
> > > > > +   pinctrl_usdhc2: usdhc2grp {
> > > > > +   fsl,pins = <
> > > > > +   MX6UL_PAD_NAND_WE_B__USDHC2_CMD  
> > > > >0x1
> > > > > 70f9
> > > > > +   MX6UL_PAD_NAND_RE_B__USDHC2_CLK  
> > > > >0x1
> > > > > 00f9
> > > > > +   MX6UL_PAD_NAND_DATA00__USDHC2_DATA0  
> > > > >0x1
> > > > > 70f9
> > > > > +   MX6UL_PAD_NAND_DATA01__USDHC2_DATA1  
> > > > >0x1
> > > > > 70f9
> > > > > +   MX6UL_PAD_NAND_DATA02__USDHC2_DATA2  
> > > > >0x1
> > > > > 70f9
> > > > > +   MX6UL_PAD_NAND_DATA03__USDHC2_DATA3  
> > > > >0x1
> > > > > 70f9
> > > > > +   MX6UL_PAD_NAND_DATA04__USDHC2_DATA4  
> > > > >0x1
> > > > > 70f9
> > > > > +   MX6UL_PAD_NAND_DATA05__USDHC2_DATA5  
> > > > >0x1
> > > > > 70f9
> > > > > +   MX6UL_PAD_NAND_DATA06__USDHC2_DATA6  
> > > > >0x1
> > > > > 70f9
> > > > > +   MX6UL_PAD_NAND_DATA07__USDHC2_DATA7  
> > > > >0x1
> > > > > 70f9
> > > > > +   >;
> > > > > +   };
> > > > > 
> > > > > If there exists pcl063 modules that have eMMC and others that
> > > > > have
> > > > > NAND
> > > > > using the same pins, then this configuration is not common
> > > > > and
> > > > > therefore shouldn't be in pcl063-common.dtsi. Is it dependent
> > > > > on
> > > > > the
> > > > > flavour of i.MX used? If so I'd suggest the gpmi config needs
> > > > > to be
> > > > > pulled out into imx6ul-phycore-segin.dts and the usdhc2
> > > > > config
> > > > > needs to
> > > > > be in imx6ull-phycore-segin.dts.
> > > >   From phytec I understand that pcl063 SoM is a common platform
> > > > for
> > > > imx6UL
> >

Re: [U-Boot] [PATCH] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM

2019-04-10 Thread Parthiban Nallathambi 

Hello Wadim,

Thanks for sharing the details.

On 4/10/19 10:35 AM, Wadim Egorov wrote:

Martyn,

On 09.04.19 12:46, Martyn Welch wrote:

On Tue, 2019-04-09 at 11:30 +0200, Parthiban Nallathambi wrote:

Hello Martyn,

On 4/9/19 10:49 AM, Martyn Welch wrote:

On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote:

Hello Martyn,

On 4/8/19 7:45 PM, Martyn Welch wrote:

On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:

diff --git a/board/phytec/pcl063/spl.c
b/board/phytec/pcl063/spl.c
index b93cd493f2..73a774645d 100644
--- a/board/phytec/pcl063/spl.c
+++ b/board/phytec/pcl063/spl.c
@@ -13,6 +13,7 @@
   #include 
   #include 
   #include 
+#include 
   #include 
   
   /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x

16 x 8
->
256MiB */
@@ -117,11 +118,32 @@ static iomux_v3_cfg_t const
usdhc1_pads[] =
{
MX6_PAD_UART1_RTS_B__USDHC1_CD_B |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
   };
   
+#ifndef CONFIG_NAND_MXS

+static iomux_v3_cfg_t const usdhc2_pads[] = {
+   MX6_PAD_NAND_RE_B__USDHC2_CLK|
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_WE_B__USDHC2_CMD|
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+#endif
+

Umm, these pins are already used a few lines up for the NAND,
via
gpmi:

I understand. But pcl063 can't co-exit with NAND and eMMC
together. I
comes
either with eMMC or NAND.

Opps, sorry, just realised that I added this comment in the wrong
place. This is in relation to the following being added to
pcl063-common.dtsi:

+
+   pinctrl_usdhc2: usdhc2grp {
+   fsl,pins = <
+   MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x1
70f9
+   MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x1
00f9
+   MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x1
70f9
+   MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x1
70f9
+   MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x1
70f9
+   MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x1
70f9
+   MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x1
70f9
+   MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x1
70f9
+   MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x1
70f9
+   MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x1
70f9
+   >;
+   };

If there exists pcl063 modules that have eMMC and others that have
NAND
using the same pins, then this configuration is not common and
therefore shouldn't be in pcl063-common.dtsi. Is it dependent on
the
flavour of i.MX used? If so I'd suggest the gpmi config needs to be
pulled out into imx6ul-phycore-segin.dts and the usdhc2 config
needs to
be in imx6ull-phycore-segin.dts.

  From phytec I understand that pcl063 SoM is a common platform for
imx6UL
and imx6ULL. This can either be shipped with eMMC or NAND, but not
both.


This is correct. There are PCL-063 SOMs with eMMC or NAND. And each
PCL-063 can be a 6UL or 6ULL.





Looking a bit deeper, this seems a little odd as the product
description suggests that NAND is provided onboard and 2 SD/SDIO/MMC
connections are provided to the edge connector of the pcl063 for
expansion.

The schematic suggests the only way they could achieve eMMC onboard
would be with an eMMC that is pin compatible with the NAND they use.


eMMC is connected via usdhc2. The usdhc2 pins conflict with the gpmi pins.




Additionally, looking at the DTBs for this board in Phytec's own kernel
tree, the only use of usdhc2 that I can see is for their WLAN expansion
board[1] and I would have expected their tree to have supported such an
option if it was available (they seem to have gone to some length to
support a lot of configurations there).

Are you sure that the eMMC is provided on the pcl063 and not off board?


eMMC is on the PCL-063 and not on a carrier board.




(CCing Wadim who might be able to shed some light on this)


So there exist a possibility that phytec can provide imx6UL with eMMC
as
well. IMO, both pinmux detailing for NAND and eMMC should still
reside
in common.dtsi.


Assuming Phytec do in fact sell a pcl0063 with eMMC on board, the DTB
describes the hardware. You've said Phytec provide the board
either with eMMC *or* NAND. The device tree, as used on a specific
board, should show either the existence of NAND or eMMC.


AFAIK, the idea was to put the muxing for both flash devices in the
pcl063-som.dtsi and keep them disabled. eMMC

Re: [U-Boot] [PATCH] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM

2019-04-10 Thread Wadim Egorov 
Martyn,

On 09.04.19 12:46, Martyn Welch wrote:
> On Tue, 2019-04-09 at 11:30 +0200, Parthiban Nallathambi wrote:
>> Hello Martyn,
>>
>> On 4/9/19 10:49 AM, Martyn Welch wrote:
>>> On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote:
 Hello Martyn,

 On 4/8/19 7:45 PM, Martyn Welch wrote:
> On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:
>> diff --git a/board/phytec/pcl063/spl.c
>> b/board/phytec/pcl063/spl.c
>> index b93cd493f2..73a774645d 100644
>> --- a/board/phytec/pcl063/spl.c
>> +++ b/board/phytec/pcl063/spl.c
>> @@ -13,6 +13,7 @@
>>   #include 
>>   #include 
>>   #include 
>> +#include 
>>   #include 
>>   
>>   /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x
>> 16 x 8
>> ->
>> 256MiB */
>> @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const
>> usdhc1_pads[] =
>> {
>>  MX6_PAD_UART1_RTS_B__USDHC1_CD_B |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>   };
>>   
>> +#ifndef CONFIG_NAND_MXS
>> +static iomux_v3_cfg_t const usdhc2_pads[] = {
>> +MX6_PAD_NAND_RE_B__USDHC2_CLK|
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_WE_B__USDHC2_CMD|
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +};
>> +#endif
>> +
> Umm, these pins are already used a few lines up for the NAND,
> via
> gpmi:
 I understand. But pcl063 can't co-exit with NAND and eMMC
 together. I
 comes
 either with eMMC or NAND.
>>> Opps, sorry, just realised that I added this comment in the wrong
>>> place. This is in relation to the following being added to
>>> pcl063-common.dtsi:
>>>
>>> +
>>> +   pinctrl_usdhc2: usdhc2grp {
>>> +   fsl,pins = <
>>> +   MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x1
>>> 70f9
>>> +   MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x1
>>> 00f9
>>> +   MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x1
>>> 70f9
>>> +   MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x1
>>> 70f9
>>> +   MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x1
>>> 70f9
>>> +   MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x1
>>> 70f9
>>> +   MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x1
>>> 70f9
>>> +   MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x1
>>> 70f9
>>> +   MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x1
>>> 70f9
>>> +   MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x1
>>> 70f9
>>> +   >;
>>> +   };
>>>
>>> If there exists pcl063 modules that have eMMC and others that have
>>> NAND
>>> using the same pins, then this configuration is not common and
>>> therefore shouldn't be in pcl063-common.dtsi. Is it dependent on
>>> the
>>> flavour of i.MX used? If so I'd suggest the gpmi config needs to be
>>> pulled out into imx6ul-phycore-segin.dts and the usdhc2 config
>>> needs to
>>> be in imx6ull-phycore-segin.dts.
>>  From phytec I understand that pcl063 SoM is a common platform for
>> imx6UL
>> and imx6ULL. This can either be shipped with eMMC or NAND, but not
>> both.

This is correct. There are PCL-063 SOMs with eMMC or NAND. And each
PCL-063 can be a 6UL or 6ULL.


>>
> Looking a bit deeper, this seems a little odd as the product
> description suggests that NAND is provided onboard and 2 SD/SDIO/MMC
> connections are provided to the edge connector of the pcl063 for
> expansion.
>
> The schematic suggests the only way they could achieve eMMC onboard
> would be with an eMMC that is pin compatible with the NAND they use.

eMMC is connected via usdhc2. The usdhc2 pins conflict with the gpmi pins.


>
> Additionally, looking at the DTBs for this board in Phytec's own kernel
> tree, the only use of usdhc2 that I can see is for their WLAN expansion
> board[1] and I would have expected their tree to have supported such an
> option if it was available (they seem to have gone to some length to
> support a lot of configurations there).
>
> Are you sure that the eMMC is provided on the pcl063 and not off board?

eMMC is on the PCL-063 and not on a carrier board.


>
> (CCing Wadim who might be able to shed some light on this)
>
>> So there exist a possibility

Re: [U-Boot] [PATCH] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM

2019-04-09 Thread Parthiban Nallathambi 

Hello Martyn,

On 4/9/19 12:46 PM, Martyn Welch wrote:

On Tue, 2019-04-09 at 11:30 +0200, Parthiban Nallathambi wrote:

Hello Martyn,

On 4/9/19 10:49 AM, Martyn Welch wrote:

On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote:

Hello Martyn,

On 4/8/19 7:45 PM, Martyn Welch wrote:

On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:

diff --git a/board/phytec/pcl063/spl.c
b/board/phytec/pcl063/spl.c
index b93cd493f2..73a774645d 100644
--- a/board/phytec/pcl063/spl.c
+++ b/board/phytec/pcl063/spl.c
@@ -13,6 +13,7 @@
   #include 
   #include 
   #include 
+#include 
   #include 
   
   /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x

16 x 8
->
256MiB */
@@ -117,11 +118,32 @@ static iomux_v3_cfg_t const
usdhc1_pads[] =
{
MX6_PAD_UART1_RTS_B__USDHC1_CD_B |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
   };
   
+#ifndef CONFIG_NAND_MXS

+static iomux_v3_cfg_t const usdhc2_pads[] = {
+   MX6_PAD_NAND_RE_B__USDHC2_CLK|
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_WE_B__USDHC2_CMD|
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+#endif
+


Umm, these pins are already used a few lines up for the NAND,
via
gpmi:


I understand. But pcl063 can't co-exit with NAND and eMMC
together. I
comes
either with eMMC or NAND.


Opps, sorry, just realised that I added this comment in the wrong
place. This is in relation to the following being added to
pcl063-common.dtsi:

+
+   pinctrl_usdhc2: usdhc2grp {
+   fsl,pins = <
+   MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x1
70f9
+   MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x1
00f9
+   MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x1
70f9
+   MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x1
70f9
+   MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x1
70f9
+   MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x1
70f9
+   MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x1
70f9
+   MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x1
70f9
+   MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x1
70f9
+   MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x1
70f9
+   >;
+   };

If there exists pcl063 modules that have eMMC and others that have
NAND
using the same pins, then this configuration is not common and
therefore shouldn't be in pcl063-common.dtsi. Is it dependent on
the
flavour of i.MX used? If so I'd suggest the gpmi config needs to be
pulled out into imx6ul-phycore-segin.dts and the usdhc2 config
needs to
be in imx6ull-phycore-segin.dts.


  From phytec I understand that pcl063 SoM is a common platform for
imx6UL
and imx6ULL. This can either be shipped with eMMC or NAND, but not
both.



Looking a bit deeper, this seems a little odd as the product
description suggests that NAND is provided onboard and 2 SD/SDIO/MMC
connections are provided to the edge connector of the pcl063 for
expansion.

The schematic suggests the only way they could achieve eMMC onboard
would be with an eMMC that is pin compatible with the NAND they use.

Additionally, looking at the DTBs for this board in Phytec's own kernel
tree, the only use of usdhc2 that I can see is for their WLAN expansion
board[1] and I would have expected their tree to have supported such an
option if it was available (they seem to have gone to some length to
support a lot of configurations there).

Are you sure that the eMMC is provided on the pcl063 and not off board?


Yes, I have this SoM with me and the changes are tested in it already.
Pinmuxing details are based on phytec's barebox which is yet to be in
mainline [1].

Phytec already published the booting from eMMC option and configurations
which are needed in the hardware level here [2].



(CCing Wadim who might be able to shed some light on this)


So there exist a possibility that phytec can provide imx6UL with eMMC
as
well. IMO, both pinmux detailing for NAND and eMMC should still
reside
in common.dtsi.



Assuming Phytec do in fact sell a pcl0063 with eMMC on board, the DTB
describes the hardware. You've said Phytec provide the board
either with eMMC *or* NAND. The device tree, as used on a specific
board, should show either the existence of NAND or eMMC.

I suspect having both options in the common file is going to lead to
issues with the pinmuxing for one or the other option. The pins can't
be muxed

Re: [U-Boot] [PATCH] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM

2019-04-09 Thread Martyn Welch 
On Tue, 2019-04-09 at 11:30 +0200, Parthiban Nallathambi wrote:
> Hello Martyn,
> 
> On 4/9/19 10:49 AM, Martyn Welch wrote:
> > On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote:
> > > Hello Martyn,
> > > 
> > > On 4/8/19 7:45 PM, Martyn Welch wrote:
> > > > On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:
> > > > > diff --git a/board/phytec/pcl063/spl.c
> > > > > b/board/phytec/pcl063/spl.c
> > > > > index b93cd493f2..73a774645d 100644
> > > > > --- a/board/phytec/pcl063/spl.c
> > > > > +++ b/board/phytec/pcl063/spl.c
> > > > > @@ -13,6 +13,7 @@
> > > > >   #include 
> > > > >   #include 
> > > > >   #include 
> > > > > +#include 
> > > > >   #include 
> > > > >   
> > > > >   /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x
> > > > > 16 x 8
> > > > > ->
> > > > > 256MiB */
> > > > > @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const
> > > > > usdhc1_pads[] =
> > > > > {
> > > > >   MX6_PAD_UART1_RTS_B__USDHC1_CD_B |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > >   };
> > > > >   
> > > > > +#ifndef CONFIG_NAND_MXS
> > > > > +static iomux_v3_cfg_t const usdhc2_pads[] = {
> > > > > + MX6_PAD_NAND_RE_B__USDHC2_CLK|
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + MX6_PAD_NAND_WE_B__USDHC2_CMD|
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > + MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
> > > > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > > > +};
> > > > > +#endif
> > > > > +
> > > > 
> > > > Umm, these pins are already used a few lines up for the NAND,
> > > > via
> > > > gpmi:
> > > 
> > > I understand. But pcl063 can't co-exit with NAND and eMMC
> > > together. I
> > > comes
> > > either with eMMC or NAND.
> > 
> > Opps, sorry, just realised that I added this comment in the wrong
> > place. This is in relation to the following being added to
> > pcl063-common.dtsi:
> > 
> > +
> > +   pinctrl_usdhc2: usdhc2grp {
> > +   fsl,pins = <
> > +   MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x1
> > 70f9
> > +   MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x1
> > 00f9
> > +   MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x1
> > 70f9
> > +   MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x1
> > 70f9
> > +   MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x1
> > 70f9
> > +   MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x1
> > 70f9
> > +   MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x1
> > 70f9
> > +   MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x1
> > 70f9
> > +   MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x1
> > 70f9
> > +   MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x1
> > 70f9
> > +   >;
> > +   };
> > 
> > If there exists pcl063 modules that have eMMC and others that have
> > NAND
> > using the same pins, then this configuration is not common and
> > therefore shouldn't be in pcl063-common.dtsi. Is it dependent on
> > the
> > flavour of i.MX used? If so I'd suggest the gpmi config needs to be
> > pulled out into imx6ul-phycore-segin.dts and the usdhc2 config
> > needs to
> > be in imx6ull-phycore-segin.dts.
> 
>  From phytec I understand that pcl063 SoM is a common platform for
> imx6UL
> and imx6ULL. This can either be shipped with eMMC or NAND, but not
> both.
> 

Looking a bit deeper, this seems a little odd as the product
description suggests that NAND is provided onboard and 2 SD/SDIO/MMC
connections are provided to the edge connector of the pcl063 for
expansion.

The schematic suggests the only way they could achieve eMMC onboard
would be with an eMMC that is pin compatible with the NAND they use.

Additionally, looking at the DTBs for this board in Phytec's own kernel
tree, the only use of usdhc2 that I can see is for their WLAN expansion
board[1] and I would have expected their tree to have supported such an
option if it was available (they seem to have gone to some length to
support a lot of configurations there).

Are you sure that the eMMC is provided on the pcl063 and not off board?

(CCing Wadim who might be able to shed some light on this)

> So there exist a possibility that phytec can provide imx6UL with eMMC
> as
> well. IMO, both pinmux detailing for NAND and eMMC should still
> reside
> in common.dtsi.
> 

Assuming Phytec do in

Re: [U-Boot] [PATCH] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM

2019-04-09 Thread Parthiban Nallathambi 

Hello Martyn,

On 4/9/19 10:49 AM, Martyn Welch wrote:

On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote:

Hello Martyn,

On 4/8/19 7:45 PM, Martyn Welch wrote:

On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:

diff --git a/board/phytec/pcl063/spl.c
b/board/phytec/pcl063/spl.c
index b93cd493f2..73a774645d 100644
--- a/board/phytec/pcl063/spl.c
+++ b/board/phytec/pcl063/spl.c
@@ -13,6 +13,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  
  /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8

->
256MiB */
@@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] =
{
MX6_PAD_UART1_RTS_B__USDHC1_CD_B |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
  };
  
+#ifndef CONFIG_NAND_MXS

+static iomux_v3_cfg_t const usdhc2_pads[] = {
+   MX6_PAD_NAND_RE_B__USDHC2_CLK|
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_WE_B__USDHC2_CMD|
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+#endif
+


Umm, these pins are already used a few lines up for the NAND, via
gpmi:


I understand. But pcl063 can't co-exit with NAND and eMMC together. I
comes
either with eMMC or NAND.


Opps, sorry, just realised that I added this comment in the wrong
place. This is in relation to the following being added to
pcl063-common.dtsi:

+
+   pinctrl_usdhc2: usdhc2grp {
+   fsl,pins = <
+   MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
+   MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
+   MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+   MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+   MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+   MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+   MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
+   MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
+   MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
+   MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
+   >;
+   };

If there exists pcl063 modules that have eMMC and others that have NAND
using the same pins, then this configuration is not common and
therefore shouldn't be in pcl063-common.dtsi. Is it dependent on the
flavour of i.MX used? If so I'd suggest the gpmi config needs to be
pulled out into imx6ul-phycore-segin.dts and the usdhc2 config needs to
be in imx6ull-phycore-segin.dts.


From phytec I understand that pcl063 SoM is a common platform for imx6UL
and imx6ULL. This can either be shipped with eMMC or NAND, but not both.

So there exist a possibility that phytec can provide imx6UL with eMMC as
well. IMO, both pinmux detailing for NAND and eMMC should still reside
in common.dtsi.

Creating multiple common.dtsi based on these variants is not friendly.
So I suggest to keep these changes in common.dtsi as such and decide in
board dts whether to enable or disable usdhc1, usdhc2 explicitly.






 pinctrl_gpmi_nand: gpminandgrp {
 fsl,pins = <
 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0
b0b1
 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0
b0b1
 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B   0x0
b0b1
 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B
0x0b000
 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0
b0b1
 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B   0x0
b0b1
 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B   0x0
b0b1
 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0
b0b1
 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0
b0b1
 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0
b0b1
 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0
b0b1
 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0
b0b1
 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0
b0b1
 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0
b0b1
 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0
b0b1
 >;
 };


  static struct fsl_esdhc_cfg usdhc_cfg[] = {
{
.esdhc_base = USDHC1_BASE_ADDR,
.max_bus_width = 4,
},
+#ifndef CONFIG_NAND_MXS
+   {
+

Re: [U-Boot] [PATCH] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM

2019-04-09 Thread Martyn Welch 
On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote:
> Hello Martyn,
> 
> On 4/8/19 7:45 PM, Martyn Welch wrote:
> > On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:
> > > diff --git a/board/phytec/pcl063/spl.c
> > > b/board/phytec/pcl063/spl.c
> > > index b93cd493f2..73a774645d 100644
> > > --- a/board/phytec/pcl063/spl.c
> > > +++ b/board/phytec/pcl063/spl.c
> > > @@ -13,6 +13,7 @@
> > >  #include 
> > >  #include 
> > >  #include 
> > > +#include 
> > >  #include 
> > >  
> > >  /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8
> > > ->
> > > 256MiB */
> > > @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] =
> > > {
> > >   MX6_PAD_UART1_RTS_B__USDHC1_CD_B |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > >  };
> > >  
> > > +#ifndef CONFIG_NAND_MXS
> > > +static iomux_v3_cfg_t const usdhc2_pads[] = {
> > > + MX6_PAD_NAND_RE_B__USDHC2_CLK|
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + MX6_PAD_NAND_WE_B__USDHC2_CMD|
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > + MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > +};
> > > +#endif
> > > +
> > 
> > Umm, these pins are already used a few lines up for the NAND, via
> > gpmi:
> 
> I understand. But pcl063 can't co-exit with NAND and eMMC together. I
> comes
> either with eMMC or NAND.

Opps, sorry, just realised that I added this comment in the wrong
place. This is in relation to the following being added to
pcl063-common.dtsi:

+
+   pinctrl_usdhc2: usdhc2grp {
+   fsl,pins = <
+   MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
+   MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
+   MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+   MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+   MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+   MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+   MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
+   MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
+   MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
+   MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
+   >;
+   };

If there exists pcl063 modules that have eMMC and others that have NAND
using the same pins, then this configuration is not common and
therefore shouldn't be in pcl063-common.dtsi. Is it dependent on the
flavour of i.MX used? If so I'd suggest the gpmi config needs to be
pulled out into imx6ul-phycore-segin.dts and the usdhc2 config needs to
be in imx6ull-phycore-segin.dts.

> 
> > pinctrl_gpmi_nand: gpminandgrp {
> > fsl,pins = <
> > MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0
> > b0b1
> > MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0
> > b0b1
> > MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B   0x0
> > b0b1
> > MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B
> > 0x0b000
> > MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0
> > b0b1
> > MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B   0x0
> > b0b1
> > MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B   0x0
> > b0b1
> > MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0
> > b0b1
> > MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0
> > b0b1
> > MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0
> > b0b1
> > MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0
> > b0b1
> > MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0
> > b0b1
> > MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0
> > b0b1
> > MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0
> > b0b1
> > MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0
> > b0b1
> > >;
> > };
> > 
> > >  static struct fsl_esdhc_cfg usdhc_cfg[] = {
> > >   {
> > >   .esdhc_base = USDHC1_BASE_ADDR,
> > >   .max_bus_width = 4,
> > >   },
> > > +#ifndef CONFIG_NAND_MXS
> > > + {
> > > + .esdhc_base = USDHC2_BASE_ADDR,
> > > + .max_bus_width = 8,
> > > + },
> > > +#endif
> > >  };
> > >  
> > >  int board_mmc_getcd(struct mmc *mmc)
> > > @@ -131,12 +153,58 @@ int board_mmc_getcd(struct mmc *mmc)
> > >

Re: [U-Boot] [PATCH] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM

2019-04-08 Thread Parthiban 
Hello Martyn,

On 4/8/19 7:45 PM, Martyn Welch wrote:
> On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:
>> diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c
>> index b93cd493f2..73a774645d 100644
>> --- a/board/phytec/pcl063/spl.c
>> +++ b/board/phytec/pcl063/spl.c
>> @@ -13,6 +13,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  
>>  /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 ->
>> 256MiB */
>> @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
>>  MX6_PAD_UART1_RTS_B__USDHC1_CD_B |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>  };
>>  
>> +#ifndef CONFIG_NAND_MXS
>> +static iomux_v3_cfg_t const usdhc2_pads[] = {
>> +MX6_PAD_NAND_RE_B__USDHC2_CLK|
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_WE_B__USDHC2_CMD|
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
>> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +};
>> +#endif
>> +
> 
> Umm, these pins are already used a few lines up for the NAND, via gpmi:

I understand. But pcl063 can't co-exit with NAND and eMMC together. I comes
either with eMMC or NAND.

> 
> pinctrl_gpmi_nand: gpminandgrp {
> fsl,pins = <
> MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
> MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
> MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B   0x0b0b1
> MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
> MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
> MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B   0x0b0b1
> MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B   0x0b0b1
> MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
> MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
> MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
> MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
> MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
> MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
> MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
> MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
> >;
> };
> 
>>  static struct fsl_esdhc_cfg usdhc_cfg[] = {
>>  {
>>  .esdhc_base = USDHC1_BASE_ADDR,
>>  .max_bus_width = 4,
>>  },
>> +#ifndef CONFIG_NAND_MXS
>> +{
>> +.esdhc_base = USDHC2_BASE_ADDR,
>> +.max_bus_width = 8,
>> +},
>> +#endif
>>  };
>>  
>>  int board_mmc_getcd(struct mmc *mmc)
>> @@ -131,12 +153,58 @@ int board_mmc_getcd(struct mmc *mmc)
>>  
>>  int board_mmc_init(bd_t *bis)
>>  {
>> -imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
>> ARRAY_SIZE(usdhc1_pads));
>> -usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
>> -
>> -return fsl_esdhc_initialize(bis, _cfg[0]);
>> +int i, ret;
>> +
>> +for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> 
> This breaks for the existing phycore_pcl063_defconfig:

Ah, I missed it. I will add CONFIG_SYS_FSL_USDHC_NUM to 1 in
phycore_pcl063_defconfig.

Thanks,
Parthiban N

> 
> board/phytec/pcl063/spl.c: In function ‘board_mmc_init’:
> board/phytec/pcl063/spl.c:158:18: error: ‘CONFIG_SYS_FSL_USDHC_NUM’
> undeclared (first use in this function); did you mean
> ‘CONFIG_SYS_FSL_ESDHC_ADDR’?
>   for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
>   ^~~~
> 
> 
> Martyn
> 
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Re: [U-Boot] [PATCH] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM

2019-04-08 Thread Martyn Welch 
On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:
> diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c
> index b93cd493f2..73a774645d 100644
> --- a/board/phytec/pcl063/spl.c
> +++ b/board/phytec/pcl063/spl.c
> @@ -13,6 +13,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  
>  /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 ->
> 256MiB */
> @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
>   MX6_PAD_UART1_RTS_B__USDHC1_CD_B |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
>  };
>  
> +#ifndef CONFIG_NAND_MXS
> +static iomux_v3_cfg_t const usdhc2_pads[] = {
> + MX6_PAD_NAND_RE_B__USDHC2_CLK|
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_WE_B__USDHC2_CMD|
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +};
> +#endif
> +

Umm, these pins are already used a few lines up for the NAND, via gpmi:

pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B   0x0b0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B   0x0b0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B   0x0b0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
>;
};

>  static struct fsl_esdhc_cfg usdhc_cfg[] = {
>   {
>   .esdhc_base = USDHC1_BASE_ADDR,
>   .max_bus_width = 4,
>   },
> +#ifndef CONFIG_NAND_MXS
> + {
> + .esdhc_base = USDHC2_BASE_ADDR,
> + .max_bus_width = 8,
> + },
> +#endif
>  };
>  
>  int board_mmc_getcd(struct mmc *mmc)
> @@ -131,12 +153,58 @@ int board_mmc_getcd(struct mmc *mmc)
>  
>  int board_mmc_init(bd_t *bis)
>  {
> - imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
> ARRAY_SIZE(usdhc1_pads));
> - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> -
> - return fsl_esdhc_initialize(bis, _cfg[0]);
> + int i, ret;
> +
> + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {

This breaks for the existing phycore_pcl063_defconfig:

board/phytec/pcl063/spl.c: In function ‘board_mmc_init’:
board/phytec/pcl063/spl.c:158:18: error: ‘CONFIG_SYS_FSL_USDHC_NUM’
undeclared (first use in this function); did you mean
‘CONFIG_SYS_FSL_ESDHC_ADDR’?
  for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  ^~~~


Martyn

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[U-Boot] [PATCH] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM

2019-04-07 Thread Parthiban Nallathambi 
Extend PHYTEC phyBOARD-i.MX6UL for phyCORE-i.MX6UL SoM (PCL063)
with eMMC on SoM.

CPU:   Freescale i.MX6ULL rev1.0 792 MHz (running at 396 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 38C
Reset cause: POR
Model: Phytec phyBOARD-i.MX6ULL-Segin SBC
Board: PHYTEC phyCORE-i.MX6ULL
DRAM:  256 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:serial@0202
Out:   serial@0202
Err:   serial@0202
Net:   FEC0

Working:
 - Eth0
 - i2C
 - MMC/SD
 - eMMC
 - UART (1 & 5)
 - USB (host & otg)

Signed-off-by: Parthiban Nallathambi 
---
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/imx6ul-phycore-segin.dts |   3 +-
 arch/arm/dts/imx6ull-phycore-segin.dts|  81 
 ...{imx6ul-pcl063.dtsi => pcl063-common.dtsi} |  31 -
 arch/arm/mach-imx/mx6/Kconfig |  12 ++
 board/phytec/pcl063/Kconfig   |  13 ++
 board/phytec/pcl063/MAINTAINERS   |   6 +-
 board/phytec/pcl063/pcl063.c  |   5 +-
 board/phytec/pcl063/spl.c |  76 +++-
 configs/phycore_pcl063_ull_defconfig  |  54 
 include/configs/pcl063_ull.h  | 117 ++
 11 files changed, 388 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/dts/imx6ull-phycore-segin.dts
 rename arch/arm/dts/{imx6ul-pcl063.dtsi => pcl063-common.dtsi} (84%)
 create mode 100644 configs/phycore_pcl063_ull_defconfig
 create mode 100644 include/configs/pcl063_ull.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0e2ffdb87f..431afb915f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -539,6 +539,7 @@ dtb-$(CONFIG_MX6UL) += \
 dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri.dtb \
+   imx6ull-phycore-segin.dtb
 
 dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7d-sdb-qspi.dtb \
diff --git a/arch/arm/dts/imx6ul-phycore-segin.dts 
b/arch/arm/dts/imx6ul-phycore-segin.dts
index a46012e2b4..9e6984e137 100644
--- a/arch/arm/dts/imx6ul-phycore-segin.dts
+++ b/arch/arm/dts/imx6ul-phycore-segin.dts
@@ -16,7 +16,8 @@
 
 /dts-v1/;
 
-#include "imx6ul-pcl063.dtsi"
+#include "imx6ul.dtsi"
+#include "pcl063-common.dtsi"
 
 / {
model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
diff --git a/arch/arm/dts/imx6ull-phycore-segin.dts 
b/arch/arm/dts/imx6ull-phycore-segin.dts
new file mode 100644
index 00..c20a867c90
--- /dev/null
+++ b/arch/arm/dts/imx6ull-phycore-segin.dts
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Parthiban Nallathambi 
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6ull.dtsi"
+#include "pcl063-common.dtsi"
+
+/ {
+   model = "Phytec phyBOARD-i.MX6ULL-Segin SBC";
+   compatible = "phytec,phyboard-imx6ull-segin", "phytec,imx6ull-pcl063",
+"fsl,imx6ull";
+};
+
+ {
+   status = "disabled";
+};
+
+ {
+   i2c_rtc: rtc@68 {
+   compatible = "microcrystal,rv4162";
+   reg = <0x68>;
+   status = "okay";
+   };
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_uart5>;
+   uart-has-rtscts;
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_usb_otg1_id>;
+   dr_mode = "otg";
+   srp-disable;
+   hnp-disable;
+   adp-disable;
+   status = "okay";
+};
+
+ {
+   dr_mode = "host";
+   disable-over-current;
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+
+   pinctrl_uart5: uart5grp {
+   fsl,pins = <
+   MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX   0x1b0b1
+   MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX   0x1b0b1
+   MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
+   MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
+   >;
+   };
+
+   pinctrl_usb_otg1_id: usbotg1idgrp {
+   fsl,pins = <
+   MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID0x17059
+   >;
+   };
+
+};
diff --git a/arch/arm/dts/imx6ul-pcl063.dtsi b/arch/arm/dts/pcl063-common.dtsi
similarity index 84%
rename from arch/arm/dts/imx6ul-pcl063.dtsi
rename to arch/arm/dts/pcl063-common.dtsi
index 24a6a47983..f505f62230 100644
--- a/arch/arm/dts/imx6ul-pcl063.dtsi
+++ b/arch/arm/dts/pcl063-common.dtsi
@@ -7,10 +7,6 @@
  * Author: Christian Hemp 
  */
 
-/dts-v1/;
-
-#include "imx6ul.dtsi"
-
 / {
model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
@@ -99,6 +95,18 @@
status = "okay";
 };
 
+ {
+   u-boot,dm-spl;
+