Re: [U-Boot] [PATCH] mmc: sunxi: Only update timing mode bit when enabling new timing mode

[Jagan Teki]

On Thu, Aug 31, 2017 at 7:36 PM, Jagan Teki  wrote:
> On Thu, Aug 31, 2017 at 7:34 PM, Maxime Ripard
>  wrote:
>> On Thu, Aug 31, 2017 at 09:57:48PM +0800, Chen-Yu Tsai wrote:
>>> When enabling the new mmc timing mode, we inadvertently clear all the
>>> remaining bits in the new timing mode register. The bits cleared
>>> include a default phase delay on the output clock. The BSP kernel
>>> states that the default values are supposed to be used. Clearing them
>>> results in decreased performance or transfer errors on some boards.
>>>
>>> Fixes: de9b1771c3b6 ("mmc: sunxi: Support new mode")
>>> Signed-off-by: Chen-Yu Tsai 
>>
>> Acked-by: Maxime Ripard 
>
> Reviewed-by: Jagan Teki 

Applied to u-boot-sunxi/master

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH] mmc: sunxi: Only update timing mode bit when enabling new timing mode

[Jagan Teki]

On Thu, Aug 31, 2017 at 7:34 PM, Maxime Ripard
 wrote:
> On Thu, Aug 31, 2017 at 09:57:48PM +0800, Chen-Yu Tsai wrote:
>> When enabling the new mmc timing mode, we inadvertently clear all the
>> remaining bits in the new timing mode register. The bits cleared
>> include a default phase delay on the output clock. The BSP kernel
>> states that the default values are supposed to be used. Clearing them
>> results in decreased performance or transfer errors on some boards.
>>
>> Fixes: de9b1771c3b6 ("mmc: sunxi: Support new mode")
>> Signed-off-by: Chen-Yu Tsai 
>
> Acked-by: Maxime Ripard 

Reviewed-by: Jagan Teki 

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH] mmc: sunxi: Only update timing mode bit when enabling new timing mode

[Maxime Ripard]

On Thu, Aug 31, 2017 at 09:57:48PM +0800, Chen-Yu Tsai wrote:
> When enabling the new mmc timing mode, we inadvertently clear all the
> remaining bits in the new timing mode register. The bits cleared
> include a default phase delay on the output clock. The BSP kernel
> states that the default values are supposed to be used. Clearing them
> results in decreased performance or transfer errors on some boards.
> 
> Fixes: de9b1771c3b6 ("mmc: sunxi: Support new mode")
> Signed-off-by: Chen-Yu Tsai 

Acked-by: Maxime Ripard 

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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[U-Boot] [PATCH] mmc: sunxi: Only update timing mode bit when enabling new timing mode

[Chen-Yu Tsai]

When enabling the new mmc timing mode, we inadvertently clear all the
remaining bits in the new timing mode register. The bits cleared
include a default phase delay on the output clock. The BSP kernel
states that the default values are supposed to be used. Clearing them
results in decreased performance or transfer errors on some boards.

Fixes: de9b1771c3b6 ("mmc: sunxi: Support new mode")
Signed-off-by: Chen-Yu Tsai 
---
 drivers/mmc/sunxi_mmc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index a76e763bfd4f..4edb4be46c81 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -167,7 +167,7 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, 
unsigned int hz)
if (new_mode) {
 #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
val = CCM_MMC_CTRL_MODE_SEL_NEW;
-   writel(SUNXI_MMC_NTSR_MODE_SEL_NEW, >reg->ntsr);
+   setbits_le32(>reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
 #endif
} else {
val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
-- 
2.14.1

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