A new deep sleep interface is introduced to support generic
board structure. Converts it to use new interface.
Besides, added SPI/SD/NAND boot deep sleep support.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
board/freescale/t102xrdb/ddr.c | 19 +++
board/freescale/t102xrdb/spl.c | 7 +++
board/freescale/t102xrdb/t102xrdb.c | 23 +++
include/configs/T102xRDB.h | 21 -
4 files changed, 49 insertions(+), 21 deletions(-)
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index a20330b..a2a8f4c 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -11,6 +11,7 @@
#include fsl_ddr_sdram.h
#include fsl_ddr_dimm_params.h
#include asm/fsl_law.h
+#include asm/mpc85xx_gpio.h
DECLARE_GLOBAL_DATA_PTR;
@@ -136,6 +137,19 @@ found:
#endif
}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+ void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(cpld_base + 0x17, 0x40);
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
+
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
@@ -150,5 +164,10 @@ phys_size_t initdram(int board_type)
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+
+#if defined(CONFIG_DEEP_SLEEP) !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
return dram_size;
}
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index dd2dec4..1a3a996 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -11,6 +11,7 @@
#include mmc.h
#include fsl_esdhc.h
#include spi_flash.h
+#include ../common/sleep.h
DECLARE_GLOBAL_DATA_PTR;
@@ -42,6 +43,12 @@ void board_init_f(ulong bootflag)
console_init_f();
+#ifdef CONFIG_DEEP_SLEEP
+ /* disable the console if boot from deep sleep */
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(gur-rcwsr[0]) 25) 0x1f;
diff --git a/board/freescale/t102xrdb/t102xrdb.c
b/board/freescale/t102xrdb/t102xrdb.c
index f5c438d..96457cf 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -16,10 +16,10 @@
#include asm/fsl_serdes.h
#include asm/fsl_portals.h
#include asm/fsl_liodn.h
-#include asm/mpc85xx_gpio.h
#include fm_eth.h
#include t102xrdb.h
#include cpld.h
+#include ../common/sleep.h
DECLARE_GLOBAL_DATA_PTR;
@@ -55,6 +55,16 @@ int checkboard(void)
return 0;
}
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
+ return 0;
+}
+
int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
@@ -131,14 +141,3 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0;
}
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
- /* does not provide HW signals for power management */
- CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) ~0x40));
- /* Disable MCKE isolation */
- gpio_set_value(2, 0);
- udelay(1);
-}
-#endif
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 82b669b..e6222f3 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -36,7 +36,10 @@
/* support deep sleep */
#define CONFIG_DEEP_SLEEP
+#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_SILENT_CONSOLE
+#define CONFIG_BOARD_EARLY_INIT_F
+#endif
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
@@ -51,7 +54,7 @@
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_FSL_LAW /* Use common FSL init code */
-#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SYS_TEXT_BASE 0x30001000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x4
#define CONFIG_SPL_MAX_SIZE0x28000
@@ -67,21 +70,21 @@
#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_SIZE(768 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x0020
-#define CONFIG_SYS_NAND_U_BOOT_START 0x0020
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x3000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x3000
#define CONFIG_SYS_NAND_U_BOOT_OFFS(256 10)
#define CONFIG_SYS_LDSCRIPTarch/powerpc/cpu/mpc85xx/u-boot-nand.lds
#define CONFIG_SPL_NAND_BOOT
#endif
#ifdef CONFIG_SPIFLASH
-#define CONFIG_RESET_VECTOR_ADDRESS0x200FFC
+#define CONFIG_RESET_VECTOR_ADDRESS0x3FFC
#define CONFIG_SPL_SPI_SUPPORT
#define
