SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384)
and at cold temperatures(A006475), workaround recalibrate the
PLLs with some SerDes configuration
Both these errata are only applicable for b4 rev1.
So, make workaround for these errata conditional,
depending upon soc version.
Signed-off-by: Shaveta Leekha shav...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |8 ++
arch/powerpc/include/asm/config_mpc85xx.h |2 +
arch/powerpc/include/asm/immap_85xx.h | 19 +++-
board/freescale/b4860qds/b4860qds.c | 193 +
4 files changed, 220 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 7693899..d0a1c51 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -229,6 +229,14 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
if (IS_SVR_REV(svr, 1, 0))
puts(Work-around for Erratum A005871 enabled\n);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006475
+ if (SVR_MAJ(get_svr()) == 1)
+ puts(Work-around for Erratum A006475 enabled\n);
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006384
+ if (SVR_MAJ(get_svr()) == 1)
+ puts(Work-around for Erratum A006384 enabled\n);
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
/* This work-around is implemented in PBI, so just check for it */
check_erratum_a4849(svr);
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 0ec1417..2f47b3f 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -662,6 +662,8 @@
#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_FSL_ERRATUM_A006379
#define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A006475
+#define CONFIG_SYS_FSL_ERRATUM_A006384
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe00
#ifdef CONFIG_PPC_B4860
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index e0efc7e..edd7888 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2495,6 +2495,7 @@ typedef struct serdes_corenet {
#define SRDS_RSTCTL_SDEN 0x0020
#define SRDS_RSTCTL_SDRST_B0x0040
#define SRDS_RSTCTL_PLLRST_B 0x0080
+#define SRDS_RSTCTL_RSTERR_SHIFT 29
u32 pllcr0; /* PLL Control Register 0 */
#define SRDS_PLLCR0_POFF 0x8000
#define SRDS_PLLCR0_RFCK_SEL_MASK 0x7000
@@ -2504,6 +2505,7 @@ typedef struct serdes_corenet {
#define SRDS_PLLCR0_RFCK_SEL_150 0x3000
#define SRDS_PLLCR0_RFCK_SEL_161_130x4000
#define SRDS_PLLCR0_RFCK_SEL_122_880x5000
+#define SRDS_PLLCR0_DCBIAS_OUT_EN 0x0200
#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f
#define SRDS_PLLCR0_FRATE_SEL_50x
#define SRDS_PLLCR0_FRATE_SEL_3_75 0x0005
@@ -2511,9 +2513,22 @@ typedef struct serdes_corenet {
#define SRDS_PLLCR0_FRATE_SEL_40x0007
#define SRDS_PLLCR0_FRATE_SEL_3_12 0x0009
#define SRDS_PLLCR0_FRATE_SEL_30x000a
+#define SRDS_PLLCR0_DCBIAS_OVRD0x00F0
+#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4
u32 pllcr1; /* PLL Control Register 1 */
-#define SRDS_PLLCR1_PLL_BWSEL 0x0800
- u32 res_0c; /* 0x00c */
+#define SRDS_PLLCR1_BCAP_EN0x2000
+#define SRDS_PLLCR1_BCAP_OVD 0x1000
+#define SRDS_PLLCR1_PLL_FCAP 0x001F8000
+#define SRDS_PLLCR1_PLL_FCAP_SHIFT 15
+#define SRDS_PLLCR1_PLL_BWSEL 0x0800
+#define SRDS_PLLCR1_BYP_CAL0x0200
+ u32 pllsr2; /* At 0x00c, PLL Status Register 2 */
+#define SRDS_PLLSR2_BCAP_EN0x0080
+#define SRDS_PLLSR2_BCAP_EN_SHIFT 23
+#define SRDS_PLLSR2_FCAP 0x003F
+#define SRDS_PLLSR2_FCAP_SHIFT 16
+#define SRDS_PLLSR2_DCBIAS 0x000F
+#define SRDS_PLLSR2_DCBIAS_SHIFT 16
u32 pllcr3;
u32 pllcr4;
u8 res_18[0x20-0x18];
diff --git a/board/freescale/b4860qds/b4860qds.c
b/board/freescale/b4860qds/b4860qds.c
index 15b3f62..264d8c7 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -286,6 +286,182 @@ int configure_vsc3316_3308(void)
return 0;
}
+static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
+{
+ u32 rst_err;
+
+ /* Steps For SerDes PLLs reset and reconfiguration
+* or PLL power-up procedure
+*/
+ debug(CALIBRATE PLL:%d\n, pll_num);
+ clrbits_be32(srds_regs-bank[pll_num].rstctl,
+ SRDS_RSTCTL_SDRST_B);
+ udelay(10);
+ clrbits_be32(srds_regs-bank[pll_num].rstctl,
+
