Re: [U-Boot] [PATCH] powerpc/t2080: DDR controller erratum A-009942

2017-01-04 Thread york sun 
On 10/26/2016 12:54 PM, Hamish Martin wrote:
>> York
> Just to clarify, should I abandon this patch because you (or someone
> else from NXP) will provide a better, more comprehensive fix?

Hamish,

New implementation of erratum workaround for A009942 is in place, see 
commit 473f1fc2 and 90101386. This patch is no longer needed.

Thanks.

York
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Re: [U-Boot] [PATCH] powerpc/t2080: DDR controller erratum A-009942

2016-11-01 Thread Shengzhou Liu 
> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of york sun
> Sent: Thursday, October 27, 2016 3:57 AM
> To: Hamish Martin <hamish.mar...@alliedtelesis.co.nz>; u-
> b...@lists.denx.de
> Subject: Re: [U-Boot] [PATCH] powerpc/t2080: DDR controller erratum A-009942
> I got a notice from our hardware team that this workaround needs a little
> change. While our DDR maintainer is on that, he may be able to add the 
> workaround to DDR3 controller as well.
> 
> York

The new patches cover all DDR3/DDR4 parts. 
http://patchwork.ozlabs.org/patch/689803  
http://patchwork.ozlabs.org/patch/689802 

-Shengzhou
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Re: [U-Boot] [PATCH] powerpc/t2080: DDR controller erratum A-009942

2016-10-26 Thread york sun 
On 10/26/2016 12:54 PM, Hamish Martin wrote:
>
> On 10/27/2016 05:33 AM, york sun wrote:
>> On 10/21/2016 04:37 PM, york sun wrote:
>>> On 10/18/2016 07:48 PM, Hamish Martin wrote:
 This erratum is already implemented for other ARM based QorIQ
 platforms with the Gen4 DDR controller. Port the fix to the Gen3
 controller and enable it for T2080 and T2081.

 Reviewed-by: Chris Packham 
 Signed-off-by: Hamish Martin 
 Cc: York Sun 
 ---
   arch/powerpc/cpu/mpc85xx/cmd_errata.c |  3 +++
   arch/powerpc/include/asm/config_mpc85xx.h |  1 +
   drivers/ddr/fsl/mpc85xx_ddr_gen3.c| 17 +
   3 files changed, 21 insertions(+)

 diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c 
 b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
 index 3b06ae42e4bc..94b6dcca96b6 100644
 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
 +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
 @@ -329,6 +329,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int 
 argc, char * const argv[])
   #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
puts("Work-around for Erratum A009663 enabled\n");
   #endif
 +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
 +  puts("Work-around for Erratum A009942 enabled\n");
 +#endif

return 0;
   }
 diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
 b/arch/powerpc/include/asm/config_mpc85xx.h
 index 6d845e859f4a..9e1cd80e16e0 100644
 --- a/arch/powerpc/include/asm/config_mpc85xx.h
 +++ b/arch/powerpc/include/asm/config_mpc85xx.h
 @@ -910,6 +910,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
   #define CONFIG_SYS_FSL_ERRATUM_A006593
   #define CONFIG_SYS_FSL_ERRATUM_A007186
   #define CONFIG_SYS_FSL_ERRATUM_A006379
 +#define CONFIG_SYS_FSL_ERRATUM_A009942
   #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
   #define CONFIG_SYS_FSL_SFP_VER_3_0

>>> Thanks for fixing it. Please also enable this workaround for T1024,
>>> T2080, T1040, B4420, B4860, T4240 (and change the subject accordingly).
>> A second thought, NXP is updating this erratum workaround. A new patch
>> will be sent out. Thanks for bring it up.
>>
>> York
> Just to clarify, should I abandon this patch because you (or someone
> else from NXP) will provide a better, more comprehensive fix?
>

Don't abandon it before a new patch is sent.

I got a notice from our hardware team that this workaround needs a 
little change. While our DDR maintainer is on that, he may be able to 
add the workaround to DDR3 controller as well.

York

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Re: [U-Boot] [PATCH] powerpc/t2080: DDR controller erratum A-009942

2016-10-26 Thread Hamish Martin 

On 10/27/2016 05:33 AM, york sun wrote:
> On 10/21/2016 04:37 PM, york sun wrote:
>> On 10/18/2016 07:48 PM, Hamish Martin wrote:
>>> This erratum is already implemented for other ARM based QorIQ
>>> platforms with the Gen4 DDR controller. Port the fix to the Gen3
>>> controller and enable it for T2080 and T2081.
>>>
>>> Reviewed-by: Chris Packham 
>>> Signed-off-by: Hamish Martin 
>>> Cc: York Sun 
>>> ---
>>>   arch/powerpc/cpu/mpc85xx/cmd_errata.c |  3 +++
>>>   arch/powerpc/include/asm/config_mpc85xx.h |  1 +
>>>   drivers/ddr/fsl/mpc85xx_ddr_gen3.c| 17 +
>>>   3 files changed, 21 insertions(+)
>>>
>>> diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c 
>>> b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
>>> index 3b06ae42e4bc..94b6dcca96b6 100644
>>> --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
>>> +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
>>> @@ -329,6 +329,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int 
>>> argc, char * const argv[])
>>>   #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
>>> puts("Work-around for Erratum A009663 enabled\n");
>>>   #endif
>>> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
>>> +   puts("Work-around for Erratum A009942 enabled\n");
>>> +#endif
>>>
>>> return 0;
>>>   }
>>> diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
>>> b/arch/powerpc/include/asm/config_mpc85xx.h
>>> index 6d845e859f4a..9e1cd80e16e0 100644
>>> --- a/arch/powerpc/include/asm/config_mpc85xx.h
>>> +++ b/arch/powerpc/include/asm/config_mpc85xx.h
>>> @@ -910,6 +910,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
>>>   #define CONFIG_SYS_FSL_ERRATUM_A006593
>>>   #define CONFIG_SYS_FSL_ERRATUM_A007186
>>>   #define CONFIG_SYS_FSL_ERRATUM_A006379
>>> +#define CONFIG_SYS_FSL_ERRATUM_A009942
>>>   #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
>>>   #define CONFIG_SYS_FSL_SFP_VER_3_0
>>>
>> Thanks for fixing it. Please also enable this workaround for T1024,
>> T2080, T1040, B4420, B4860, T4240 (and change the subject accordingly).
> A second thought, NXP is updating this erratum workaround. A new patch
> will be sent out. Thanks for bring it up.
>
> York
Just to clarify, should I abandon this patch because you (or someone 
else from NXP) will provide a better, more comprehensive fix?

Thanks,
Hamish M.
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Re: [U-Boot] [PATCH] powerpc/t2080: DDR controller erratum A-009942

2016-10-26 Thread york sun 
On 10/21/2016 04:37 PM, york sun wrote:
> On 10/18/2016 07:48 PM, Hamish Martin wrote:
>> This erratum is already implemented for other ARM based QorIQ
>> platforms with the Gen4 DDR controller. Port the fix to the Gen3
>> controller and enable it for T2080 and T2081.
>>
>> Reviewed-by: Chris Packham 
>> Signed-off-by: Hamish Martin 
>> Cc: York Sun 
>> ---
>>  arch/powerpc/cpu/mpc85xx/cmd_errata.c |  3 +++
>>  arch/powerpc/include/asm/config_mpc85xx.h |  1 +
>>  drivers/ddr/fsl/mpc85xx_ddr_gen3.c| 17 +
>>  3 files changed, 21 insertions(+)
>>
>> diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c 
>> b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
>> index 3b06ae42e4bc..94b6dcca96b6 100644
>> --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
>> +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
>> @@ -329,6 +329,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int 
>> argc, char * const argv[])
>>  #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
>>  puts("Work-around for Erratum A009663 enabled\n");
>>  #endif
>> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
>> +puts("Work-around for Erratum A009942 enabled\n");
>> +#endif
>>
>>  return 0;
>>  }
>> diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
>> b/arch/powerpc/include/asm/config_mpc85xx.h
>> index 6d845e859f4a..9e1cd80e16e0 100644
>> --- a/arch/powerpc/include/asm/config_mpc85xx.h
>> +++ b/arch/powerpc/include/asm/config_mpc85xx.h
>> @@ -910,6 +910,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
>>  #define CONFIG_SYS_FSL_ERRATUM_A006593
>>  #define CONFIG_SYS_FSL_ERRATUM_A007186
>>  #define CONFIG_SYS_FSL_ERRATUM_A006379
>> +#define CONFIG_SYS_FSL_ERRATUM_A009942
>>  #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
>>  #define CONFIG_SYS_FSL_SFP_VER_3_0
>>
>
> Thanks for fixing it. Please also enable this workaround for T1024,
> T2080, T1040, B4420, B4860, T4240 (and change the subject accordingly).

A second thought, NXP is updating this erratum workaround. A new patch 
will be sent out. Thanks for bring it up.

York
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Re: [U-Boot] [PATCH] powerpc/t2080: DDR controller erratum A-009942

2016-10-21 Thread york sun 
On 10/18/2016 07:48 PM, Hamish Martin wrote:
> This erratum is already implemented for other ARM based QorIQ
> platforms with the Gen4 DDR controller. Port the fix to the Gen3
> controller and enable it for T2080 and T2081.
>
> Reviewed-by: Chris Packham 
> Signed-off-by: Hamish Martin 
> Cc: York Sun 
> ---
>  arch/powerpc/cpu/mpc85xx/cmd_errata.c |  3 +++
>  arch/powerpc/include/asm/config_mpc85xx.h |  1 +
>  drivers/ddr/fsl/mpc85xx_ddr_gen3.c| 17 +
>  3 files changed, 21 insertions(+)
>
> diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c 
> b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> index 3b06ae42e4bc..94b6dcca96b6 100644
> --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> @@ -329,6 +329,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int 
> argc, char * const argv[])
>  #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
>   puts("Work-around for Erratum A009663 enabled\n");
>  #endif
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
> + puts("Work-around for Erratum A009942 enabled\n");
> +#endif
>
>   return 0;
>  }
> diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
> b/arch/powerpc/include/asm/config_mpc85xx.h
> index 6d845e859f4a..9e1cd80e16e0 100644
> --- a/arch/powerpc/include/asm/config_mpc85xx.h
> +++ b/arch/powerpc/include/asm/config_mpc85xx.h
> @@ -910,6 +910,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
>  #define CONFIG_SYS_FSL_ERRATUM_A006593
>  #define CONFIG_SYS_FSL_ERRATUM_A007186
>  #define CONFIG_SYS_FSL_ERRATUM_A006379
> +#define CONFIG_SYS_FSL_ERRATUM_A009942
>  #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
>  #define CONFIG_SYS_FSL_SFP_VER_3_0
>

Thanks for fixing it. Please also enable this workaround for T1024, 
T2080, T1040, B4420, B4860, T4240 (and change the subject accordingly).

York

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[U-Boot] [PATCH] powerpc/t2080: DDR controller erratum A-009942

2016-10-18 Thread Hamish Martin 
This erratum is already implemented for other ARM based QorIQ
platforms with the Gen4 DDR controller. Port the fix to the Gen3
controller and enable it for T2080 and T2081.

Reviewed-by: Chris Packham 
Signed-off-by: Hamish Martin 
Cc: York Sun 
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c |  3 +++
 arch/powerpc/include/asm/config_mpc85xx.h |  1 +
 drivers/ddr/fsl/mpc85xx_ddr_gen3.c| 17 +
 3 files changed, 21 insertions(+)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c 
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 3b06ae42e4bc..94b6dcca96b6 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -329,6 +329,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
puts("Work-around for Erratum A009663 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+   puts("Work-around for Erratum A009942 enabled\n");
+#endif
 
return 0;
 }
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 6d845e859f4a..9e1cd80e16e0 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -910,6 +910,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A009942
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c 
b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 653b7f0c770c..a4377f80 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -39,6 +39,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
u32 save1, save2;
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+   ulong ddr_freq;
+   u32 tmp;
+#endif
 
switch (ctrl_num) {
case 0:
@@ -183,6 +187,19 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t 
*regs,
out_be32(>debug[21], 0x2400);
 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+   ddr_freq = get_ddr_freq(ctrl_num) / 100;
+   tmp = in_be32(>debug[28]);
+   if (ddr_freq <= 1333)
+   out_be32(>debug[28], tmp | 0x0080006a);
+   else if (ddr_freq <= 1600)
+   out_be32(>debug[28], tmp | 0x0070006f);
+   else if (ddr_freq <= 1867)
+   out_be32(>debug[28], tmp | 0x00700076);
+   else if (ddr_freq <= 2133)
+   out_be32(>debug[28], tmp | 0x0060007b);
+#endif
+
/*
 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 * deasserted. Clocks start when any chip select is enabled and clock
-- 
2.10.1

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