Re: [U-Boot] [PATCH] powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram

2017-04-18 Thread York Sun 

On 03/01/2017 07:37 PM, Ruchika Gupta wrote:

Fir E6500 cores, L2 cache has been used as init_ram. L1 cache is a write
through cache on E6500.If lines are not locked in both L1 and L2 caches,
crashes are observed during secure boot. This patch locks/unlocks both L1
as well as L2 cache to prevent the crash.

Signed-off-by: Ruchika Gupta 
---



Reformatted commit message to wrap back at or before 70 characters. 
Please do the same on your future patches.


Applied to u-boot-fsl-qoriq master, awaiting upstream. Thanks.

York

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Re: [U-Boot] [PATCH] powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram

2017-03-27 Thread Ruchika Gupta 


> -Original Message-
> From: york sun
> Sent: Saturday, March 25, 2017 10:16 PM
> To: Ruchika Gupta <ruchika.gu...@nxp.com>; u-boot@lists.denx.de;
> prabhakar.khushw...@nxp.com
> Subject: Re: [U-Boot] [PATCH] powerpc: e6500: Lock/unlock 1 cache instead
> of L1 as init_ram
> 
> On 03/01/2017 07:37 PM, Ruchika Gupta wrote:
> > Fir E6500 cores, L2 cache has been used as init_ram. L1 cache is a
> > write through cache on E6500.If lines are not locked in both L1 and L2
> > caches, crashes are observed during secure boot. This patch
> > locks/unlocks both L1 as well as L2 cache to prevent the crash.
> 
> I didn't even know you could/should lock L1. Any reason why it would crash?
> 
> York
In secure boot scenarios, L2 cache is also locked by Rom for usage and then 
cleared before exiting ROM. Some castouts were being observed when only L2 
cache lines were being locked in uboot hinting that lines were probably not 
getting locked. The e6500 core expert suggested to try locking in both the 
caches. This seems to resolve the crashed which we were observing. 

Ruchika

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Re: [U-Boot] [PATCH] powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram

2017-03-25 Thread york sun 
On 03/01/2017 07:37 PM, Ruchika Gupta wrote:
> Fir E6500 cores, L2 cache has been used as init_ram. L1 cache is a write
> through cache on E6500.If lines are not locked in both L1 and L2 caches,
> crashes are observed during secure boot. This patch locks/unlocks both L1
> as well as L2 cache to prevent the crash.

I didn't even know you could/should lock L1. Any reason why it would crash?

York
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[U-Boot] [PATCH] powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram

2017-03-01 Thread Ruchika Gupta 
Fir E6500 cores, L2 cache has been used as init_ram. L1 cache is a write
through cache on E6500.If lines are not locked in both L1 and L2 caches,
crashes are observed during secure boot. This patch locks/unlocks both L1
as well as L2 cache to prevent the crash.

Signed-off-by: Ruchika Gupta 
---
 arch/powerpc/cpu/mpc85xx/start.S | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index c3e1234..b9a4cb5 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1145,8 +1145,9 @@ switch_as:
li  r0,0
 1:
dcbzr0,r3
-#ifdef CONFIG_E6500/* Lock/unlock L2 cache instead of L1 */
+#ifdef CONFIG_E6500/* Lock/unlock L2 cache long with L1 */
dcbtls  2, r0, r3
+   dcbtls  0, r0, r3
 #else
dcbtls  0, r0, r3
 #endif
@@ -1790,8 +1791,9 @@ unlock_ram_in_cache:
slwir4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr   r4
 1: dcbir0,r3
-#ifdef CONFIG_E6500/* lock/unlock L2 cache instead of L1 */
+#ifdef CONFIG_E6500/* lock/unlock L2 cache long with L1 */
dcblc   2, r0, r3
+   dcblc   0, r0, r3
 #else
dcblc   r0,r3
 #endif
-- 
1.9.1

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[U-Boot] [PATCH] powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram

2017-03-01 Thread Ruchika Gupta 
Fir E6500 cores, L2 cache has been used as init_ram. L1 cache is a write
through cache on E6500.If lines are not locked in both L1 and L2 caches,
crashes are observed during secure boot. This patch locks/unlocks both L1
as well as L2 cache to prevent the crash.

Signed-off-by: Ruchika Gupta 
---
 arch/powerpc/cpu/mpc85xx/start.S | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index c3e1234..b9a4cb5 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1145,8 +1145,9 @@ switch_as:
li  r0,0
 1:
dcbzr0,r3
-#ifdef CONFIG_E6500/* Lock/unlock L2 cache instead of L1 */
+#ifdef CONFIG_E6500/* Lock/unlock L2 cache long with L1 */
dcbtls  2, r0, r3
+   dcbtls  0, r0, r3
 #else
dcbtls  0, r0, r3
 #endif
@@ -1790,8 +1791,9 @@ unlock_ram_in_cache:
slwir4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr   r4
 1: dcbir0,r3
-#ifdef CONFIG_E6500/* lock/unlock L2 cache instead of L1 */
+#ifdef CONFIG_E6500/* lock/unlock L2 cache long with L1 */
dcblc   2, r0, r3
+   dcblc   0, r0, r3
 #else
dcblc   r0,r3
 #endif
-- 
1.9.1

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