Re: [U-Boot] [PATCH] rockchip: rk3399: init CPU clock when rkclk_init()

[Simon Glass]

On 12 October 2017 at 09:27, Kever Yang  wrote:
> Init the CPU and its buses to speed up the boot time.
> Move rkclk_init() to a place after rk3399_configure_cpu has defined
> at the same time, or else there will be a warning.
>
> Signed-off-by: Kever Yang 
> ---
>
>  drivers/clk/rockchip/clk_rk3399.c | 157 
> +++---
>  1 file changed, 79 insertions(+), 78 deletions(-)

Reviewed-by: Simon Glass 
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[U-Boot] [PATCH] rockchip: rk3399: init CPU clock when rkclk_init()

[Kever Yang]

Init the CPU and its buses to speed up the boot time.
Move rkclk_init() to a place after rk3399_configure_cpu has defined
at the same time, or else there will be a warning.

Signed-off-by: Kever Yang 
---

 drivers/clk/rockchip/clk_rk3399.c | 157 +++---
 1 file changed, 79 insertions(+), 78 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3399.c 
b/drivers/clk/rockchip/clk_rk3399.c
index 50faf5d..b9b1ead 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -398,84 +398,6 @@ static int pll_para_config(u32 freq_hz, struct pll_div 
*div)
return 0;
 }
 
-#ifdef CONFIG_SPL_BUILD
-static void rkclk_init(struct rk3399_cru *cru)
-{
-   u32 aclk_div;
-   u32 hclk_div;
-   u32 pclk_div;
-
-   /*
-* some cru registers changed by bootrom, we'd better reset them to
-* reset/default values described in TRM to avoid confusion in kernel.
-* Please consider these three lines as a fix of bootrom bug.
-*/
-   rk_clrsetreg(>clksel_con[12], 0x, 0x4101);
-   rk_clrsetreg(>clksel_con[19], 0x, 0x033f);
-   rk_clrsetreg(>clksel_con[56], 0x0003, 0x0003);
-
-   /* configure gpll cpll */
-   rkclk_set_pll(>gpll_con[0], _init_cfg);
-   rkclk_set_pll(>cpll_con[0], _init_cfg);
-
-   /* configure perihp aclk, hclk, pclk */
-   aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
-   assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
-
-   hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
-   assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
-  PERIHP_ACLK_HZ && (hclk_div < 0x4));
-
-   pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
-   assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
-  PERIHP_ACLK_HZ && (pclk_div < 0x7));
-
-   rk_clrsetreg(>clksel_con[14],
-PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
-ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
-pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
-hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
-ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
-aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
-
-   /* configure perilp0 aclk, hclk, pclk */
-   aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
-   assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
-
-   hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
-   assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
-  PERILP0_ACLK_HZ && (hclk_div < 0x4));
-
-   pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
-   assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
-  PERILP0_ACLK_HZ && (pclk_div < 0x7));
-
-   rk_clrsetreg(>clksel_con[23],
-PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
-ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
-pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
-hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
-ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
-aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
-
-   /* perilp1 hclk select gpll as source */
-   hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
-   assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
-  GPLL_HZ && (hclk_div < 0x1f));
-
-   pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
-   assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
-  PERILP1_HCLK_HZ && (hclk_div < 0x7));
-
-   rk_clrsetreg(>clksel_con[25],
-PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
-HCLK_PERILP1_PLL_SEL_MASK,
-pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
-hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
-HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
-}
-#endif
-
 void rk3399_configure_cpu(struct rk3399_cru *cru,
  enum apll_l_frequencies apll_l_freq)
 {
@@ -1004,6 +926,85 @@ static struct clk_ops rk3399_clk_ops = {
.enable = rk3399_clk_enable,
 };
 
+#ifdef CONFIG_SPL_BUILD
+static void rkclk_init(struct rk3399_cru *cru)
+{
+   u32 aclk_div;
+   u32 hclk_div;
+   u32 pclk_div;
+
+   rk3399_configure_cpu(cru, APLL_L_600_MHZ);
+   /*
+* some cru registers changed by bootrom, we'd better reset them to
+* reset/default values described in TRM to avoid confusion in kernel.
+* Please consider these three lines as a fix of bootrom bug.
+*/
+   rk_clrsetreg(>clksel_con[12], 0x, 0x4101);
+   rk_clrsetreg(>clksel_con[19], 0x, 0x033f);
+   rk_clrsetreg(>clksel_con[56], 0x0003, 0x0003);
+
+   /* configure gpll cpll */
+   rkclk_set_pll(>gpll_con[0], _init_cfg);
+   rkclk_set_pll(>cpll_con[0], _init_cfg);
+
+   /* configure