Re: [U-Boot] [PATCH 04/22] x86: Add a x86_ prefix to the x86-specific PCI functions
On Thu, Feb 19, 2015 at 5:10 AM, Simon Glass s...@chromium.org wrote:
These functions currently use a generic name, but they are for x86 only.
This may introduce confusion and prevents U-Boot from using these names
more widely.
In fact it should be possible to remove these at some point and use
generic functions, but for now, rename them.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/baytrail/early_uart.c | 5 ++-
arch/x86/cpu/ivybridge/bd82x6x.c | 32 +++---
arch/x86/cpu/ivybridge/cpu.c | 38
arch/x86/cpu/ivybridge/early_init.c | 58 +
arch/x86/cpu/ivybridge/early_me.c| 12 +++---
arch/x86/cpu/ivybridge/gma.c | 4 +-
arch/x86/cpu/ivybridge/lpc.c | 74
arch/x86/cpu/ivybridge/northbridge.c | 6 +--
arch/x86/cpu/ivybridge/pch.c | 4 +-
arch/x86/cpu/ivybridge/pci.c | 4 +-
arch/x86/cpu/ivybridge/report_platform.c | 4 +-
arch/x86/cpu/ivybridge/sata.c| 61 +-
arch/x86/cpu/ivybridge/sdram.c | 20 -
arch/x86/cpu/ivybridge/usb_ehci.c| 4 +-
arch/x86/cpu/ivybridge/usb_xhci.c| 8 ++--
arch/x86/cpu/pci.c | 12 +++---
arch/x86/cpu/quark/quark.c | 4 +-
arch/x86/cpu/queensbay/tnc.c | 4 +-
arch/x86/include/asm/pci.h | 12 +++---
arch/x86/lib/bios_interrupts.c | 12 +++---
drivers/gpio/intel_ich6_gpio.c | 16 +++
21 files changed, 199 insertions(+), 195 deletions(-)
diff --git a/arch/x86/cpu/baytrail/early_uart.c
b/arch/x86/cpu/baytrail/early_uart.c
index 4199210..b64a3a9 100644
--- a/arch/x86/cpu/baytrail/early_uart.c
+++ b/arch/x86/cpu/baytrail/early_uart.c
@@ -50,7 +50,7 @@ static void score_select_func(int pad, int func)
writel(reg, pconf0_addr);
}
-static void pci_write_config32(int dev, unsigned int where, u32 value)
+static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
{
unsigned long addr;
@@ -62,7 +62,8 @@ static void pci_write_config32(int dev, unsigned int where,
u32 value)
int setup_early_uart(void)
{
/* Enable the legacy UART hardware. */
- pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT,
1);
+ x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC),
UART_CONT,
+ 1);
/*
* Set up the pads to the UART function. This allows the signals to
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c
b/arch/x86/cpu/ivybridge/bd82x6x.c
index 65a17d3..56b19e3 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -22,36 +22,36 @@ void bd82x6x_pci_init(pci_dev_t dev)
debug(bd82x6x PCI init.\n);
/* Enable Bus Master */
- reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
reg16 |= PCI_COMMAND_MASTER;
- pci_write_config16(dev, PCI_COMMAND, reg16);
+ x86_pci_write_config16(dev, PCI_COMMAND, reg16);
/* This device has no interrupt */
- pci_write_config8(dev, INTR, 0xff);
+ x86_pci_write_config8(dev, INTR, 0xff);
/* disable parity error response and SERR */
- reg16 = pci_read_config16(dev, BCTRL);
+ reg16 = x86_pci_read_config16(dev, BCTRL);
reg16 = ~(1 0);
reg16 = ~(1 1);
- pci_write_config16(dev, BCTRL, reg16);
+ x86_pci_write_config16(dev, BCTRL, reg16);
/* Master Latency Count must be set to 0x04! */
- reg8 = pci_read_config8(dev, SMLT);
+ reg8 = x86_pci_read_config8(dev, SMLT);
reg8 = 0x07;
reg8 |= (0x04 3);
- pci_write_config8(dev, SMLT, reg8);
+ x86_pci_write_config8(dev, SMLT, reg8);
/* Will this improve throughput of bus masters? */
- pci_write_config8(dev, PCI_MIN_GNT, 0x06);
+ x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06);
/* Clear errors in status registers */
- reg16 = pci_read_config16(dev, PSTS);
+ reg16 = x86_pci_read_config16(dev, PSTS);
/* reg16 |= 0xf900; */
- pci_write_config16(dev, PSTS, reg16);
+ x86_pci_write_config16(dev, PSTS, reg16);
- reg16 = pci_read_config16(dev, SECSTS);
+ reg16 = x86_pci_read_config16(dev, SECSTS);
/* reg16 |= 0xf900; */
- pci_write_config16(dev, SECSTS, reg16);
+ x86_pci_write_config16(dev, SECSTS, reg16);
}
#define PCI_BRIDGE_UPDATE_COMMAND
@@ -59,7 +59,7 @@ void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
{
uint16_t command;
- command = pci_read_config16(dev, PCI_COMMAND);
+ command = x86_pci_read_config16(dev, PCI_COMMAND);
command |= PCI_COMMAND_IO;
#ifdef PCI_BRIDGE_UPDATE_COMMAND
/*
@@ -67,7 +67,7 @@
[U-Boot] [PATCH 04/22] x86: Add a x86_ prefix to the x86-specific PCI functions
These functions currently use a generic name, but they are for x86 only.
This may introduce confusion and prevents U-Boot from using these names
more widely.
In fact it should be possible to remove these at some point and use
generic functions, but for now, rename them.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/baytrail/early_uart.c | 5 ++-
arch/x86/cpu/ivybridge/bd82x6x.c | 32 +++---
arch/x86/cpu/ivybridge/cpu.c | 38
arch/x86/cpu/ivybridge/early_init.c | 58 +
arch/x86/cpu/ivybridge/early_me.c| 12 +++---
arch/x86/cpu/ivybridge/gma.c | 4 +-
arch/x86/cpu/ivybridge/lpc.c | 74
arch/x86/cpu/ivybridge/northbridge.c | 6 +--
arch/x86/cpu/ivybridge/pch.c | 4 +-
arch/x86/cpu/ivybridge/pci.c | 4 +-
arch/x86/cpu/ivybridge/report_platform.c | 4 +-
arch/x86/cpu/ivybridge/sata.c| 61 +-
arch/x86/cpu/ivybridge/sdram.c | 20 -
arch/x86/cpu/ivybridge/usb_ehci.c| 4 +-
arch/x86/cpu/ivybridge/usb_xhci.c| 8 ++--
arch/x86/cpu/pci.c | 12 +++---
arch/x86/cpu/quark/quark.c | 4 +-
arch/x86/cpu/queensbay/tnc.c | 4 +-
arch/x86/include/asm/pci.h | 12 +++---
arch/x86/lib/bios_interrupts.c | 12 +++---
drivers/gpio/intel_ich6_gpio.c | 16 +++
21 files changed, 199 insertions(+), 195 deletions(-)
diff --git a/arch/x86/cpu/baytrail/early_uart.c
b/arch/x86/cpu/baytrail/early_uart.c
index 4199210..b64a3a9 100644
--- a/arch/x86/cpu/baytrail/early_uart.c
+++ b/arch/x86/cpu/baytrail/early_uart.c
@@ -50,7 +50,7 @@ static void score_select_func(int pad, int func)
writel(reg, pconf0_addr);
}
-static void pci_write_config32(int dev, unsigned int where, u32 value)
+static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
{
unsigned long addr;
@@ -62,7 +62,8 @@ static void pci_write_config32(int dev, unsigned int where,
u32 value)
int setup_early_uart(void)
{
/* Enable the legacy UART hardware. */
- pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, 1);
+ x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT,
+ 1);
/*
* Set up the pads to the UART function. This allows the signals to
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 65a17d3..56b19e3 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -22,36 +22,36 @@ void bd82x6x_pci_init(pci_dev_t dev)
debug(bd82x6x PCI init.\n);
/* Enable Bus Master */
- reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
reg16 |= PCI_COMMAND_MASTER;
- pci_write_config16(dev, PCI_COMMAND, reg16);
+ x86_pci_write_config16(dev, PCI_COMMAND, reg16);
/* This device has no interrupt */
- pci_write_config8(dev, INTR, 0xff);
+ x86_pci_write_config8(dev, INTR, 0xff);
/* disable parity error response and SERR */
- reg16 = pci_read_config16(dev, BCTRL);
+ reg16 = x86_pci_read_config16(dev, BCTRL);
reg16 = ~(1 0);
reg16 = ~(1 1);
- pci_write_config16(dev, BCTRL, reg16);
+ x86_pci_write_config16(dev, BCTRL, reg16);
/* Master Latency Count must be set to 0x04! */
- reg8 = pci_read_config8(dev, SMLT);
+ reg8 = x86_pci_read_config8(dev, SMLT);
reg8 = 0x07;
reg8 |= (0x04 3);
- pci_write_config8(dev, SMLT, reg8);
+ x86_pci_write_config8(dev, SMLT, reg8);
/* Will this improve throughput of bus masters? */
- pci_write_config8(dev, PCI_MIN_GNT, 0x06);
+ x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06);
/* Clear errors in status registers */
- reg16 = pci_read_config16(dev, PSTS);
+ reg16 = x86_pci_read_config16(dev, PSTS);
/* reg16 |= 0xf900; */
- pci_write_config16(dev, PSTS, reg16);
+ x86_pci_write_config16(dev, PSTS, reg16);
- reg16 = pci_read_config16(dev, SECSTS);
+ reg16 = x86_pci_read_config16(dev, SECSTS);
/* reg16 |= 0xf900; */
- pci_write_config16(dev, SECSTS, reg16);
+ x86_pci_write_config16(dev, SECSTS, reg16);
}
#define PCI_BRIDGE_UPDATE_COMMAND
@@ -59,7 +59,7 @@ void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
{
uint16_t command;
- command = pci_read_config16(dev, PCI_COMMAND);
+ command = x86_pci_read_config16(dev, PCI_COMMAND);
command |= PCI_COMMAND_IO;
#ifdef PCI_BRIDGE_UPDATE_COMMAND
/*
@@ -67,7 +67,7 @@ void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
* ROM and APICs to become invisible.
*/
debug(%x cmd - %02x\n, dev, command);
-
