Re: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Marek Vasut]

On 12/19/2016 10:30 AM, Chee, Tien Fong wrote:
> On Isn, 2016-12-19 at 08:47 +0100, Marek Vasut wrote:
>> On 12/19/2016 07:53 AM, Chee, Tien Fong wrote:
>>>
>>> On Jum, 2016-12-09 at 13:51 +0100, Marek Vasut wrote:

 On 12/09/2016 11:04 AM, Chee, Tien Fong wrote:
>
>
> On Rab, 2016-12-07 at 14:58 +0100, Marek Vasut wrote:
>>
>>
>> On 12/07/2016 12:58 PM, Chee, Tien Fong wrote:
>>>
>>>
>>>
>>> On Sel, 2016-12-06 at 13:55 +0100, Marek Vasut wrote:



 On 12/06/2016 09:08 AM, Chee Tien Fong wrote:
>
>
>
>
> From: Tien Fong Chee 
>
> Drivers for reset manager is restructured such that
> common
> functions,
> gen5 drivers and Arria10 drivers are moved to
> reset_manager.c,
> reset_manager_gen5.c and reset_manager_arria10.c
> respectively.
>
> Signed-off-by: Tien Fong Chee >
> Cc: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> Cc: Tien Fong 
>> [...]
>>
>>>
>>>
>>>



>
>
>
> +void reset_deassert_dedicated_peripherals(void)
> +{
> + int i;
> + u32 mask0 = 0;
> + u32 mask1 = 0;
> + u32 pinmux_addr =
> SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS;
> + u32 mask = 0;
> +#if defined(CONFIG_MMC)
> + mask |=
> ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
> +#elif defined(CONFIG_CADENCE_QSPI)
> + mask |= ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK;
> +#elif defined(CONFIG_NAND_DENALI)
> + mask |= ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK;
> +#else
 Shouldn't this come from OF instead of being ifdef'd ?

>>> What is OF?
>> Device Tree (Open Firmware).
>>
>>>
>>>
>>>
>>> what is your suggestion to make this function generic for
>>> all type of flash?
>> Pull it from OF ?
>>
> Why you prefer device tree implementation over #define in
> defconfig,
> because there is performance penalty.
 Because we are moving away from excessive random #defines and
 toward
 having one single binary where you could exchange just the DT and
 run
 it on multiple boards, just like Linux, that is the ultimate
 goal.

 Also, this is not performance critical code, is it.

>>> This code just to release peripherals from reset, not performance
>>> critical codes. However, our defconfigs based on flash type
>>> booting, so
>>> this is why i din't use the DT, since we have flash type determined
>>> from defconfig. Since DT is ultimate goal, i can change to DT
>>> implementation.
>> You should really only unreset the peripherals which you need and,
>> ideally, only when you need them. So it should be the driver which
>> handles the peripheral reset, not the common code (unless there is
>> a reason for the common code to do it).
>>
> Yeah, i agree with you too. Did our cyclone5 implement this also?
> Does DM has framework to support  user define reset mechanism?

The CV does it at least for ethernet . I don't think there is a
dedicated mechanism yet.

-- 
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Chee, Tien Fong]

On Isn, 2016-12-19 at 08:47 +0100, Marek Vasut wrote:
> On 12/19/2016 07:53 AM, Chee, Tien Fong wrote:
> > 
> > On Jum, 2016-12-09 at 13:51 +0100, Marek Vasut wrote:
> > > 
> > > On 12/09/2016 11:04 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Rab, 2016-12-07 at 14:58 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 12/07/2016 12:58 PM, Chee, Tien Fong wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On Sel, 2016-12-06 at 13:55 +0100, Marek Vasut wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On 12/06/2016 09:08 AM, Chee Tien Fong wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > From: Tien Fong Chee 
> > > > > > > > 
> > > > > > > > Drivers for reset manager is restructured such that
> > > > > > > > common
> > > > > > > > functions,
> > > > > > > > gen5 drivers and Arria10 drivers are moved to
> > > > > > > > reset_manager.c,
> > > > > > > > reset_manager_gen5.c and reset_manager_arria10.c
> > > > > > > > respectively.
> > > > > > > > 
> > > > > > > > Signed-off-by: Tien Fong Chee  > > > > > > > >
> > > > > > > > Cc: Marek Vasut 
> > > > > > > > Cc: Dinh Nguyen 
> > > > > > > > Cc: Chin Liang See 
> > > > > > > > Cc: Tien Fong 
> > > > > [...]
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > +void reset_deassert_dedicated_peripherals(void)
> > > > > > > > +{
> > > > > > > > +   int i;
> > > > > > > > +   u32 mask0 = 0;
> > > > > > > > +   u32 mask1 = 0;
> > > > > > > > +   u32 pinmux_addr =
> > > > > > > > SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS;
> > > > > > > > +   u32 mask = 0;
> > > > > > > > +#if defined(CONFIG_MMC)
> > > > > > > > +   mask |=
> > > > > > > > ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
> > > > > > > > +#elif defined(CONFIG_CADENCE_QSPI)
> > > > > > > > +   mask |= ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK;
> > > > > > > > +#elif defined(CONFIG_NAND_DENALI)
> > > > > > > > +   mask |= ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK;
> > > > > > > > +#else
> > > > > > > Shouldn't this come from OF instead of being ifdef'd ?
> > > > > > > 
> > > > > > What is OF?
> > > > > Device Tree (Open Firmware).
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > what is your suggestion to make this function generic for
> > > > > > all type of flash?
> > > > > Pull it from OF ?
> > > > > 
> > > > Why you prefer device tree implementation over #define in
> > > > defconfig,
> > > > because there is performance penalty.
> > > Because we are moving away from excessive random #defines and
> > > toward
> > > having one single binary where you could exchange just the DT and
> > > run
> > > it on multiple boards, just like Linux, that is the ultimate
> > > goal.
> > > 
> > > Also, this is not performance critical code, is it.
> > > 
> > This code just to release peripherals from reset, not performance
> > critical codes. However, our defconfigs based on flash type
> > booting, so
> > this is why i din't use the DT, since we have flash type determined
> > from defconfig. Since DT is ultimate goal, i can change to DT
> > implementation.
> You should really only unreset the peripherals which you need and,
> ideally, only when you need them. So it should be the driver which
> handles the peripheral reset, not the common code (unless there is
> a reason for the common code to do it).
> 
Yeah, i agree with you too. Did our cyclone5 implement this also?
Does DM has framework to support  user define reset mechanism?
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Marek Vasut]

On 12/19/2016 07:53 AM, Chee, Tien Fong wrote:
> On Jum, 2016-12-09 at 13:51 +0100, Marek Vasut wrote:
>> On 12/09/2016 11:04 AM, Chee, Tien Fong wrote:
>>>
>>> On Rab, 2016-12-07 at 14:58 +0100, Marek Vasut wrote:

 On 12/07/2016 12:58 PM, Chee, Tien Fong wrote:
>
>
> On Sel, 2016-12-06 at 13:55 +0100, Marek Vasut wrote:
>>
>>
>> On 12/06/2016 09:08 AM, Chee Tien Fong wrote:
>>>
>>>
>>>
>>> From: Tien Fong Chee 
>>>
>>> Drivers for reset manager is restructured such that common
>>> functions,
>>> gen5 drivers and Arria10 drivers are moved to
>>> reset_manager.c,
>>> reset_manager_gen5.c and reset_manager_arria10.c
>>> respectively.
>>>
>>> Signed-off-by: Tien Fong Chee 
>>> Cc: Marek Vasut 
>>> Cc: Dinh Nguyen 
>>> Cc: Chin Liang See 
>>> Cc: Tien Fong 
 [...]

>
>
>>
>>
>>>
>>>
>>> +void reset_deassert_dedicated_peripherals(void)
>>> +{
>>> +   int i;
>>> +   u32 mask0 = 0;
>>> +   u32 mask1 = 0;
>>> +   u32 pinmux_addr =
>>> SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS;
>>> +   u32 mask = 0;
>>> +#if defined(CONFIG_MMC)
>>> +   mask |= ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
>>> +#elif defined(CONFIG_CADENCE_QSPI)
>>> +   mask |= ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK;
>>> +#elif defined(CONFIG_NAND_DENALI)
>>> +   mask |= ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK;
>>> +#else
>> Shouldn't this come from OF instead of being ifdef'd ?
>>
> What is OF?
 Device Tree (Open Firmware).

>
>
> what is your suggestion to make this function generic for
> all type of flash?
 Pull it from OF ?

>>> Why you prefer device tree implementation over #define in
>>> defconfig,
>>> because there is performance penalty.
>> Because we are moving away from excessive random #defines and toward
>> having one single binary where you could exchange just the DT and run
>> it on multiple boards, just like Linux, that is the ultimate goal.
>>
>> Also, this is not performance critical code, is it.
>>
> This code just to release peripherals from reset, not performance
> critical codes. However, our defconfigs based on flash type booting, so
> this is why i din't use the DT, since we have flash type determined
> from defconfig. Since DT is ultimate goal, i can change to DT
> implementation.

You should really only unreset the peripherals which you need and,
ideally, only when you need them. So it should be the driver which
handles the peripheral reset, not the common code (unless there is
a reason for the common code to do it).

-- 
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Chee, Tien Fong]

On Jum, 2016-12-09 at 13:51 +0100, Marek Vasut wrote:
> On 12/09/2016 11:04 AM, Chee, Tien Fong wrote:
> > 
> > On Rab, 2016-12-07 at 14:58 +0100, Marek Vasut wrote:
> > > 
> > > On 12/07/2016 12:58 PM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Sel, 2016-12-06 at 13:55 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 12/06/2016 09:08 AM, Chee Tien Fong wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > From: Tien Fong Chee 
> > > > > > 
> > > > > > Drivers for reset manager is restructured such that common
> > > > > > functions,
> > > > > > gen5 drivers and Arria10 drivers are moved to
> > > > > > reset_manager.c,
> > > > > > reset_manager_gen5.c and reset_manager_arria10.c
> > > > > > respectively.
> > > > > > 
> > > > > > Signed-off-by: Tien Fong Chee 
> > > > > > Cc: Marek Vasut 
> > > > > > Cc: Dinh Nguyen 
> > > > > > Cc: Chin Liang See 
> > > > > > Cc: Tien Fong 
> > > [...]
> > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > +void reset_deassert_dedicated_peripherals(void)
> > > > > > +{
> > > > > > +   int i;
> > > > > > +   u32 mask0 = 0;
> > > > > > +   u32 mask1 = 0;
> > > > > > +   u32 pinmux_addr =
> > > > > > SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS;
> > > > > > +   u32 mask = 0;
> > > > > > +#if defined(CONFIG_MMC)
> > > > > > +   mask |= ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
> > > > > > +#elif defined(CONFIG_CADENCE_QSPI)
> > > > > > +   mask |= ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK;
> > > > > > +#elif defined(CONFIG_NAND_DENALI)
> > > > > > +   mask |= ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK;
> > > > > > +#else
> > > > > Shouldn't this come from OF instead of being ifdef'd ?
> > > > > 
> > > > What is OF?
> > > Device Tree (Open Firmware).
> > > 
> > > > 
> > > > 
> > > > what is your suggestion to make this function generic for
> > > > all type of flash?
> > > Pull it from OF ?
> > > 
> > Why you prefer device tree implementation over #define in
> > defconfig,
> > because there is performance penalty.
> Because we are moving away from excessive random #defines and toward
> having one single binary where you could exchange just the DT and run
> it on multiple boards, just like Linux, that is the ultimate goal.
> 
> Also, this is not performance critical code, is it.
> 
This code just to release peripherals from reset, not performance
critical codes. However, our defconfigs based on flash type booting, so
this is why i din't use the DT, since we have flash type determined
from defconfig. Since DT is ultimate goal, i can change to DT
implementation.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Marek Vasut]

On 12/09/2016 11:04 AM, Chee, Tien Fong wrote:
> On Rab, 2016-12-07 at 14:58 +0100, Marek Vasut wrote:
>> On 12/07/2016 12:58 PM, Chee, Tien Fong wrote:
>>>
>>> On Sel, 2016-12-06 at 13:55 +0100, Marek Vasut wrote:

 On 12/06/2016 09:08 AM, Chee Tien Fong wrote:
>
>
> From: Tien Fong Chee 
>
> Drivers for reset manager is restructured such that common
> functions,
> gen5 drivers and Arria10 drivers are moved to reset_manager.c,
> reset_manager_gen5.c and reset_manager_arria10.c respectively.
>
> Signed-off-by: Tien Fong Chee 
> Cc: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> Cc: Tien Fong 
>> [...]
>>
>>>

>
> +void reset_deassert_dedicated_peripherals(void)
> +{
> + int i;
> + u32 mask0 = 0;
> + u32 mask1 = 0;
> + u32 pinmux_addr = SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS;
> + u32 mask = 0;
> +#if defined(CONFIG_MMC)
> + mask |= ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
> +#elif defined(CONFIG_CADENCE_QSPI)
> + mask |= ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK;
> +#elif defined(CONFIG_NAND_DENALI)
> + mask |= ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK;
> +#else
 Shouldn't this come from OF instead of being ifdef'd ?

>>> What is OF?
>> Device Tree (Open Firmware).
>>
>>>
>>> what is your suggestion to make this function generic for
>>> all type of flash?
>> Pull it from OF ?
>>
> Why you prefer device tree implementation over #define in defconfig,
> because there is performance penalty.

Because we are moving away from excessive random #defines and toward
having one single binary where you could exchange just the DT and run
it on multiple boards, just like Linux, that is the ultimate goal.

Also, this is not performance critical code, is it.

-- 
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Chee, Tien Fong]

On Rab, 2016-12-07 at 14:58 +0100, Marek Vasut wrote:
> On 12/07/2016 12:58 PM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2016-12-06 at 13:55 +0100, Marek Vasut wrote:
> > > 
> > > On 12/06/2016 09:08 AM, Chee Tien Fong wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee 
> > > > 
> > > > Drivers for reset manager is restructured such that common
> > > > functions,
> > > > gen5 drivers and Arria10 drivers are moved to reset_manager.c,
> > > > reset_manager_gen5.c and reset_manager_arria10.c respectively.
> > > > 
> > > > Signed-off-by: Tien Fong Chee 
> > > > Cc: Marek Vasut 
> > > > Cc: Dinh Nguyen 
> > > > Cc: Chin Liang See 
> > > > Cc: Tien Fong 
> [...]
> 
> > 
> > > 
> > > > 
> > > > +void reset_deassert_dedicated_peripherals(void)
> > > > +{
> > > > +   int i;
> > > > +   u32 mask0 = 0;
> > > > +   u32 mask1 = 0;
> > > > +   u32 pinmux_addr = SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS;
> > > > +   u32 mask = 0;
> > > > +#if defined(CONFIG_MMC)
> > > > +   mask |= ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
> > > > +#elif defined(CONFIG_CADENCE_QSPI)
> > > > +   mask |= ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK;
> > > > +#elif defined(CONFIG_NAND_DENALI)
> > > > +   mask |= ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK;
> > > > +#else
> > > Shouldn't this come from OF instead of being ifdef'd ?
> > > 
> > What is OF?
> Device Tree (Open Firmware).
> 
> > 
> > what is your suggestion to make this function generic for
> > all type of flash?
> Pull it from OF ?
> 
Why you prefer device tree implementation over #define in defconfig,
because there is performance penalty.
> > 
> > > 
> > > > 
> > > > +#error "unsupported dedicated peripherals"
> > > > +#endif
> > > > +   mask |= ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK;
> > > > +
> > > > +   /* enable ECC OCP first */
> > > > +   clrbits_le32(_manager_base->per0modrst, mask);
> > > [...]
> 
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Marek Vasut]

On 12/07/2016 12:58 PM, Chee, Tien Fong wrote:
> On Sel, 2016-12-06 at 13:55 +0100, Marek Vasut wrote:
>> On 12/06/2016 09:08 AM, Chee Tien Fong wrote:
>>>
>>> From: Tien Fong Chee 
>>>
>>> Drivers for reset manager is restructured such that common
>>> functions,
>>> gen5 drivers and Arria10 drivers are moved to reset_manager.c,
>>> reset_manager_gen5.c and reset_manager_arria10.c respectively.
>>>
>>> Signed-off-by: Tien Fong Chee 
>>> Cc: Marek Vasut 
>>> Cc: Dinh Nguyen 
>>> Cc: Chin Liang See 
>>> Cc: Tien Fong 

[...]

>>> +void reset_deassert_dedicated_peripherals(void)
>>> +{
>>> +   int i;
>>> +   u32 mask0 = 0;
>>> +   u32 mask1 = 0;
>>> +   u32 pinmux_addr = SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS;
>>> +   u32 mask = 0;
>>> +#if defined(CONFIG_MMC)
>>> +   mask |= ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
>>> +#elif defined(CONFIG_CADENCE_QSPI)
>>> +   mask |= ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK;
>>> +#elif defined(CONFIG_NAND_DENALI)
>>> +   mask |= ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK;
>>> +#else
>> Shouldn't this come from OF instead of being ifdef'd ?
>>
> What is OF?

Device Tree (Open Firmware).

> what is your suggestion to make this function generic for
> all type of flash?

Pull it from OF ?

>>> +#error "unsupported dedicated peripherals"
>>> +#endif
>>> +   mask |= ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK;
>>> +
>>> +   /* enable ECC OCP first */
>>> +   clrbits_le32(_manager_base->per0modrst, mask);
>> [...]


-- 
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Chee, Tien Fong]

On Sel, 2016-12-06 at 13:55 +0100, Marek Vasut wrote:
> On 12/06/2016 09:08 AM, Chee Tien Fong wrote:
> > 
> > From: Tien Fong Chee 
> > 
> > Drivers for reset manager is restructured such that common
> > functions,
> > gen5 drivers and Arria10 drivers are moved to reset_manager.c,
> > reset_manager_gen5.c and reset_manager_arria10.c respectively.
> > 
> > Signed-off-by: Tien Fong Chee 
> > Cc: Marek Vasut 
> > Cc: Dinh Nguyen 
> > Cc: Chin Liang See 
> > Cc: Tien Fong 
> > ---
> >  arch/arm/mach-socfpga/Makefile |   16 +-
> >  arch/arm/mach-socfpga/include/mach/reset_manager.h |  164 --
> >  arch/arm/mach-socfpga/reset_manager.c  |  114 +---
> >  arch/arm/mach-socfpga/reset_manager_arria10.c  |  766
> > 
> >  arch/arm/mach-socfpga/reset_manager_gen5.c |  116 +++
> >  5 files changed, 1017 insertions(+), 159 deletions(-)
> >  create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
> >  create mode 100644 arch/arm/mach-socfpga/reset_manager_gen5.c
> > 
> > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> > socfpga/Makefile
> > index 809cd47..b8fcf6e 100644
> > --- a/arch/arm/mach-socfpga/Makefile
> > +++ b/arch/arm/mach-socfpga/Makefile
> > @@ -2,21 +2,27 @@
> >  # (C) Copyright 2000-2003
> >  # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
> >  #
> > -# Copyright (C) 2012 Altera Corporation 
> > +# Copyright (C) 2012-2016 Altera Corporation 
> >  #
> >  # SPDX-License-Identifier: GPL-2.0+
> >  #
> >  
> >  obj-y  += misc.o timer.o reset_manager.o system_manager.o
> > clock_manager.o \
> >        fpga_manager.o board.o
> > +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
> > +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o
> > wrap_pll_config.o \
> > +   reset_manager_gen5.o
> >  
> > -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> > +ifdef CONFIG_SPL_BUILD
> > +obj-y += spl.o
> > +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o
> > wrap_iocsr_config.o \
> > +   wrap_pinmux_config.o
> > wrap_sdram_config.o
> > +endif
> >  
> > +ifdef CONFIG_TARGET_SOCFPGA_GEN5
> >  # QTS-generated config file wrappers
> > -obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o
> > wrap_pll_config.o
> > -obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o
> > wrap_pinmux_config.o\
> > -      wrap_sdram_config.o
> >  CFLAGS_wrap_iocsr_config.o +=
> > -I$(srctree)/board/$(BOARDDIR)
> >  CFLAGS_wrap_pinmux_config.o+=
> > -I$(srctree)/board/$(BOARDDIR)
> >  CFLAGS_wrap_pll_config.o   += -I$(srctree)/board/$(BOARDDIR)
> >  CFLAGS_wrap_sdram_config.o +=
> > -I$(srctree)/board/$(BOARDDIR)
> > +endif
> > diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > index 6225118..077391a 100644
> > --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > @@ -1,19 +1,32 @@
> >  /*
> > - *  Copyright (C) 2012 Altera Corporation 
> > + *  Copyright (C) 2012-2016 Altera Corporation 
> >   *
> > - * SPDX-License-Identifier:GPL-2.0+
> > + * SPDX-License-Identifier:GPL-2.0
> License change ?
> 
i will revert it.
> > 
> >   */
> >  
> >  #ifndef_RESET_MANAGER_H_
> >  #define_RESET_MANAGER_H_
> >  
> > -void reset_cpu(ulong addr);
> > -void reset_deassert_peripherals_handoff(void);
> > +/* Common function prototypes */
> > +extern void reset_cpu(ulong addr);
> > +extern void socfpga_bridges_reset(int enable);
> > +extern void socfpga_per_reset(u32 reset, int set);
> > +extern void socfpga_per_reset_all(void);
> Drop the extern ...
> 
okay.
> > 
> > -void socfpga_bridges_reset(int enable);
> > -
> > -void socfpga_per_reset(u32 reset, int set);
> > -void socfpga_per_reset_all(void);
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > +extern void reset_deassert_peripherals_handoff(void);
> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +extern void watchdog_disable(void);
> > +extern void reset_deassert_noc_ddr_scheduler(void);
> > +extern int is_wdt_in_reset(void);
> > +extern void emac_manage_reset(ulong emacbase, uint state);
> > +extern int reset_deassert_bridges_handoff(void);
> > +extern void reset_deassert_dedicated_peripherals(void);
> > +extern void reset_assert_fpga_connected_peripherals(void);
> > +extern void reset_deassert_fpga_connected_peripherals(void);
> > +extern void reset_deassert_shared_connected_peripherals(void);
> > +extern void reset_deassert_osc1wd0(void);
> > +#endif
> >  
> >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >  struct socfpga_reset_manager {
> > @@ -29,40 +42,40 @@ struct socfpga_reset_manager {
> >     u32 padding2[12];
> >     u32 tstscratch;
> >  };
> > -#else
> > +#elif 

Re: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Marek Vasut]

On 12/06/2016 09:08 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee 
> 
> Drivers for reset manager is restructured such that common functions,
> gen5 drivers and Arria10 drivers are moved to reset_manager.c,
> reset_manager_gen5.c and reset_manager_arria10.c respectively.
> 
> Signed-off-by: Tien Fong Chee 
> Cc: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> Cc: Tien Fong 
> ---
>  arch/arm/mach-socfpga/Makefile |   16 +-
>  arch/arm/mach-socfpga/include/mach/reset_manager.h |  164 --
>  arch/arm/mach-socfpga/reset_manager.c  |  114 +---
>  arch/arm/mach-socfpga/reset_manager_arria10.c  |  766 
> 
>  arch/arm/mach-socfpga/reset_manager_gen5.c |  116 +++
>  5 files changed, 1017 insertions(+), 159 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
>  create mode 100644 arch/arm/mach-socfpga/reset_manager_gen5.c
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 809cd47..b8fcf6e 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -2,21 +2,27 @@
>  # (C) Copyright 2000-2003
>  # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
>  #
> -# Copyright (C) 2012 Altera Corporation 
> +# Copyright (C) 2012-2016 Altera Corporation 
>  #
>  # SPDX-License-Identifier:   GPL-2.0+
>  #
>  
>  obj-y+= misc.o timer.o reset_manager.o system_manager.o 
> clock_manager.o \
>  fpga_manager.o board.o
> +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
> +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
> + reset_manager_gen5.o
>  
> -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o wrap_iocsr_config.o 
> \
> + wrap_pinmux_config.o wrap_sdram_config.o
> +endif
>  
> +ifdef CONFIG_TARGET_SOCFPGA_GEN5
>  # QTS-generated config file wrappers
> -obj-$(CONFIG_TARGET_SOCFPGA_GEN5)+= scan_manager.o wrap_pll_config.o
> -obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o  \
> -wrap_sdram_config.o
>  CFLAGS_wrap_iocsr_config.o   += -I$(srctree)/board/$(BOARDDIR)
>  CFLAGS_wrap_pinmux_config.o  += -I$(srctree)/board/$(BOARDDIR)
>  CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR)
>  CFLAGS_wrap_sdram_config.o   += -I$(srctree)/board/$(BOARDDIR)
> +endif
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
> b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> index 6225118..077391a 100644
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> @@ -1,19 +1,32 @@
>  /*
> - *  Copyright (C) 2012 Altera Corporation 
> + *  Copyright (C) 2012-2016 Altera Corporation 
>   *
> - * SPDX-License-Identifier:  GPL-2.0+
> + * SPDX-License-Identifier:  GPL-2.0

License change ?

>   */
>  
>  #ifndef  _RESET_MANAGER_H_
>  #define  _RESET_MANAGER_H_
>  
> -void reset_cpu(ulong addr);
> -void reset_deassert_peripherals_handoff(void);
> +/* Common function prototypes */
> +extern void reset_cpu(ulong addr);
> +extern void socfpga_bridges_reset(int enable);
> +extern void socfpga_per_reset(u32 reset, int set);
> +extern void socfpga_per_reset_all(void);

Drop the extern ...

> -void socfpga_bridges_reset(int enable);
> -
> -void socfpga_per_reset(u32 reset, int set);
> -void socfpga_per_reset_all(void);
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> +extern void reset_deassert_peripherals_handoff(void);
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +extern void watchdog_disable(void);
> +extern void reset_deassert_noc_ddr_scheduler(void);
> +extern int is_wdt_in_reset(void);
> +extern void emac_manage_reset(ulong emacbase, uint state);
> +extern int reset_deassert_bridges_handoff(void);
> +extern void reset_deassert_dedicated_peripherals(void);
> +extern void reset_assert_fpga_connected_peripherals(void);
> +extern void reset_deassert_fpga_connected_peripherals(void);
> +extern void reset_deassert_shared_connected_peripherals(void);
> +extern void reset_deassert_osc1wd0(void);
> +#endif
>  
>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  struct socfpga_reset_manager {
> @@ -29,40 +42,40 @@ struct socfpga_reset_manager {
>   u32 padding2[12];
>   u32 tstscratch;
>  };
> -#else
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>  struct socfpga_reset_manager {
> - u32 stat;
> - u32 ramstat;
> - u32 miscstat;
> - u32 ctrl;
> - u32 hdsken;
> - u32 hdskreq;
> - u32 hdskack;
> - u32 counts;
> - u32 mpu_mod_reset;
> - u32 per_mod_reset;  /* stated as per0_mod_reset in A10 datasheet */
> -   

[U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Chee Tien Fong]

From: Tien Fong Chee 

Drivers for reset manager is restructured such that common functions,
gen5 drivers and Arria10 drivers are moved to reset_manager.c,
reset_manager_gen5.c and reset_manager_arria10.c respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/Makefile |   16 +-
 arch/arm/mach-socfpga/include/mach/reset_manager.h |  164 --
 arch/arm/mach-socfpga/reset_manager.c  |  114 +---
 arch/arm/mach-socfpga/reset_manager_arria10.c  |  766 
 arch/arm/mach-socfpga/reset_manager_gen5.c |  116 +++
 5 files changed, 1017 insertions(+), 159 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
 create mode 100644 arch/arm/mach-socfpga/reset_manager_gen5.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 809cd47..b8fcf6e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -2,21 +2,27 @@
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 #
-# Copyright (C) 2012 Altera Corporation 
+# Copyright (C) 2012-2016 Altera Corporation 
 #
 # SPDX-License-Identifier: GPL-2.0+
 #
 
 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
   fpga_manager.o board.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
+   reset_manager_gen5.o
 
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o wrap_iocsr_config.o \
+   wrap_pinmux_config.o wrap_sdram_config.o
+endif
 
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o
-obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
-  wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pinmux_config.o+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pll_config.o   += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
+endif
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6225118..077391a 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -1,19 +1,32 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
- * SPDX-License-Identifier:GPL-2.0+
+ * SPDX-License-Identifier:GPL-2.0
  */
 
 #ifndef_RESET_MANAGER_H_
 #define_RESET_MANAGER_H_
 
-void reset_cpu(ulong addr);
-void reset_deassert_peripherals_handoff(void);
+/* Common function prototypes */
+extern void reset_cpu(ulong addr);
+extern void socfpga_bridges_reset(int enable);
+extern void socfpga_per_reset(u32 reset, int set);
+extern void socfpga_per_reset_all(void);
 
-void socfpga_bridges_reset(int enable);
-
-void socfpga_per_reset(u32 reset, int set);
-void socfpga_per_reset_all(void);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+extern void reset_deassert_peripherals_handoff(void);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+extern void watchdog_disable(void);
+extern void reset_deassert_noc_ddr_scheduler(void);
+extern int is_wdt_in_reset(void);
+extern void emac_manage_reset(ulong emacbase, uint state);
+extern int reset_deassert_bridges_handoff(void);
+extern void reset_deassert_dedicated_peripherals(void);
+extern void reset_assert_fpga_connected_peripherals(void);
+extern void reset_deassert_fpga_connected_peripherals(void);
+extern void reset_deassert_shared_connected_peripherals(void);
+extern void reset_deassert_osc1wd0(void);
+#endif
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_reset_manager {
@@ -29,40 +42,40 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
 };
-#else
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 struct socfpga_reset_manager {
-   u32 stat;
-   u32 ramstat;
-   u32 miscstat;
-   u32 ctrl;
-   u32 hdsken;
-   u32 hdskreq;
-   u32 hdskack;
-   u32 counts;
-   u32 mpu_mod_reset;
-   u32 per_mod_reset;  /* stated as per0_mod_reset in A10 datasheet */
-   u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */
-   u32 brg_mod_reset;
-   u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */
-   u32 coldmodrst;
-   u32 nrstmodrst;
-   u32 dbgmodrst;
-   u32