Re: [U-Boot] [PATCH 06/15] drivers/qe: Change QE RISC ALLOCATION to support 4 RISCs

[Wolfgang Denk]

Dear Haiying Wang,

In message <1242837043-8243-6-git-send-email-haiying.w...@freescale.com> you 
wrote:
> Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and
> define MAX_QE_RISC for QE based silicons.
> 
> Signed-off-by: Haiying Wang 
> Acked-by: Timur Tabi 
...
> +#if (MAX_QE_RISC == 4)
> + .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS,
> + .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS,
> +#else
>   .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
>   .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
> +#endif

Is there a chance to get rid of these camel-case identifiers? They
violate the CodingStyle

Best regards,

Wolfgang Denk

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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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[U-Boot] [PATCH 06/15] drivers/qe: Change QE RISC ALLOCATION to support 4 RISCs

[Haiying Wang]

Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and
define MAX_QE_RISC for QE based silicons.

Signed-off-by: Haiying Wang 
Acked-by: Timur Tabi 
---
 drivers/qe/qe.c|3 ---
 drivers/qe/qe.h|   17 +++--
 drivers/qe/uec.c   |   32 +++-
 drivers/qe/uec.h   |4 ++--
 include/asm-ppc/immap_qe.h |8 
 5 files changed, 52 insertions(+), 12 deletions(-)

diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index f114fe0..30fe726 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -258,9 +258,6 @@ int qe_set_mii_clk_src(int ucc_num)
return 0;
 }
 
-/* The maximum number of RISCs we support */
-#define MAX_QE_RISC 2
-
 /* Firmware information stored here for qe_get_firmware_info() */
 static struct qe_firmware_info qe_firmware_info;
 
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index d78edba..2128f56 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
  *
  * Dave Liu 
  * based on source code of Shlomi Gridish
@@ -46,11 +46,16 @@ typedef struct qe_snum {
 
 /* QE RISC allocation
 */
-typedef enum qe_risc_allocation {
-   QE_RISC_ALLOCATION_RISC1= 1,  /* RISC 1 */
-   QE_RISC_ALLOCATION_RISC2= 2,  /* RISC 2 */
-   QE_RISC_ALLOCATION_RISC1_AND_RISC2  = 3   /* RISC 1 or RISC 2 */
-} qe_risc_allocation_e;
+#defineQE_RISC_ALLOCATION_RISC10x1  /* RISC 1 */
+#defineQE_RISC_ALLOCATION_RISC20x2  /* RISC 2 */
+#defineQE_RISC_ALLOCATION_RISC30x4  /* RISC 3 */
+#defineQE_RISC_ALLOCATION_RISC40x8  /* RISC 4 */
+#defineQE_RISC_ALLOCATION_RISC1_AND_RISC2  
(QE_RISC_ALLOCATION_RISC1 | \
+QE_RISC_ALLOCATION_RISC2)
+#defineQE_RISC_ALLOCATION_FOUR_RISCS   (QE_RISC_ALLOCATION_RISC1 | \
+QE_RISC_ALLOCATION_RISC2 | \
+QE_RISC_ALLOCATION_RISC3 | \
+QE_RISC_ALLOCATION_RISC4)
 
 /* QE CECR commands for UCC fast.
 */
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index bba3ef2..eadcc2c 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
  *
  * Dave Liu 
  *
@@ -46,8 +46,13 @@ static uec_info_t eth1_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
 #endif
+#if (MAX_QE_RISC == 4)
+   .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS,
+   .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC1_PHY_ADDR,
@@ -69,8 +74,13 @@ static uec_info_t eth2_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
 #endif
+#if (MAX_QE_RISC == 4)
+   .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS,
+   .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC2_PHY_ADDR,
@@ -92,8 +102,13 @@ static uec_info_t eth3_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
 #endif
+#if (MAX_QE_RISC == 4)
+   .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS,
+   .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC3_PHY_ADDR,
@@ -115,8 +130,13 @@ static uec_info_t eth4_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
 #endif
+#if (MAX_QE_RISC == 4)
+   .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS,
+   .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address