Re: [U-Boot] [PATCH 06/20] arm: socfpga: add reset driver support for Arria 10

[Marek Vasut]

On 02/28/2017 09:27 AM, Ley Foon Tan wrote:
> On Mon, Feb 27, 2017 at 6:14 PM, Ley Foon Tan  wrote:
>> On Sab, 2017-02-25 at 22:28 +0100, Marek Vasut wrote:
>>> On 02/22/2017 10:47 AM, Ley Foon Tan wrote:

 Add reset driver support for Arria 10.

 Signed-off-by: Tien Fong Chee 
 Signed-off-by: Ley Foon Tan 
 ---
  arch/arm/mach-socfpga/Makefile |   2 +
  arch/arm/mach-socfpga/include/mach/reset_manager.h |   4 +-
  .../include/mach/reset_manager_arria10.h   | 144 
  arch/arm/mach-socfpga/reset_manager_arria10.c  | 406
 +
  include/dt-bindings/reset/altr,rst-mgr-a10.h   | 103 ++
  5 files changed, 658 insertions(+), 1 deletion(-)
  create mode 100755 arch/arm/mach-
 socfpga/include/mach/reset_manager_arria10.h
  create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
  create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

 diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
 socfpga/Makefile
 index e83da2e..d81f003 100644
 --- a/arch/arm/mach-socfpga/Makefile
 +++ b/arch/arm/mach-socfpga/Makefile
 @@ -10,6 +10,8 @@
  obj-y  += misc.o timer.o reset_manager.o clock_manager.o \
fpga_manager.o board.o

 +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
 +
  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o

  # QTS-generated config file wrappers
 diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
 b/arch/arm/mach-socfpga/include/mach/reset_manager.h
 index 9e253bf..64526b6 100644
 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
 +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
 @@ -43,7 +43,9 @@ void socfpga_per_reset_all(void);
  /* Create a human-readable reference to SoCFPGA reset. */
  #define SOCFPGA_RESET(_name)   RSTMGR_##_name

 -#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 +#include 
 +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>> You can use #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) instead to
>>> keep
>>> this list sorted.
>> You want sort with GEN5, ARRIA10 or sorted alphanumerically ARRIA10
>> then GEN5?
>>>

  #include 
  #endif

 diff --git a/arch/arm/mach-
 socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-
 socfpga/include/mach/reset_manager_arria10.h
 new file mode 100755
 index 000..2668a86
 --- /dev/null
 +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
 @@ -0,0 +1,144 @@
 +/*
 + *  Copyright (C) 2012-2017 Altera Corporation 
 + *
 + * SPDX-License-Identifier:GPL-2.0+
 + */
 +
 +#ifndef_RESET_MANAGER_ARRIA10_H_
 +#define_RESET_MANAGER_ARRIA10_H_
>>> Use #ifdef[space]FOO and #define[space]FOO
>> Okay
>>>

 +void watchdog_disable(void);
 +void reset_deassert_noc_ddr_scheduler(void);
 +int is_wdt_in_reset(void);
 +void emac_manage_reset(ulong emacbase, uint state);
 +int reset_deassert_bridges_handoff(void);
 +void reset_assert_fpga_connected_peripherals(void);
 +void reset_deassert_osc1wd0(void);
 +void reset_assert_uart(void);
 +void reset_deassert_uart(void);
>>> [...]
>>>

 +#endif /* _RESET_MANAGER_ARRIA10_H_ */
 diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c
 b/arch/arm/mach-socfpga/reset_manager_arria10.c
 new file mode 100644
 index 000..01156de
 --- /dev/null
 +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
 @@ -0,0 +1,406 @@
 +/*
 + * Copyright (C) 2016-2017 Intel Corporation
 + *
 + * SPDX-License-Identifier:GPL-2.0
 + */
 +
 +#include 
 +#include 
 +#include 
 +#include 
 +#include 
 +#include 
 +#include 
 +#include 
 +
 +DECLARE_GLOBAL_DATA_PTR;
 +
 +static const struct socfpga_reset_manager *reset_manager_base =
 +   (void *)SOCFPGA_RSTMGR_ADDRESS;
 +static const struct socfpga_system_manager *sysmgr_regs =
 +   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>>> Use the tabs consistently, one or two, but pick one.
>> Okay.
>>>

 +static int get_bridge_init_val(const void *blob, int compat_id);
 +
 +#define ECC_MASK (ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK|\
 +   ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK|\
 +   ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK|\
 +   ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK|\
 +   ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK|\
 +   ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK)
>>> MSK | \
>>>
>>> Keep the spacing please.
>> Okay.
>>>

 +void reset_assert_uart(void)
 +{
 +   u32 mask = 0;
 +   unsigned int com_port;
 +
 +   com_port = 

Re: [U-Boot] [PATCH 06/20] arm: socfpga: add reset driver support for Arria 10

[Ley Foon Tan]

On Mon, Feb 27, 2017 at 6:14 PM, Ley Foon Tan  wrote:
> On Sab, 2017-02-25 at 22:28 +0100, Marek Vasut wrote:
>> On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
>> >
>> > Add reset driver support for Arria 10.
>> >
>> > Signed-off-by: Tien Fong Chee 
>> > Signed-off-by: Ley Foon Tan 
>> > ---
>> >  arch/arm/mach-socfpga/Makefile |   2 +
>> >  arch/arm/mach-socfpga/include/mach/reset_manager.h |   4 +-
>> >  .../include/mach/reset_manager_arria10.h   | 144 
>> >  arch/arm/mach-socfpga/reset_manager_arria10.c  | 406
>> > +
>> >  include/dt-bindings/reset/altr,rst-mgr-a10.h   | 103 ++
>> >  5 files changed, 658 insertions(+), 1 deletion(-)
>> >  create mode 100755 arch/arm/mach-
>> > socfpga/include/mach/reset_manager_arria10.h
>> >  create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
>> >  create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h
>> >
>> > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
>> > socfpga/Makefile
>> > index e83da2e..d81f003 100644
>> > --- a/arch/arm/mach-socfpga/Makefile
>> > +++ b/arch/arm/mach-socfpga/Makefile
>> > @@ -10,6 +10,8 @@
>> >  obj-y  += misc.o timer.o reset_manager.o clock_manager.o \
>> >fpga_manager.o board.o
>> >
>> > +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
>> > +
>> >  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
>> >
>> >  # QTS-generated config file wrappers
>> > diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
>> > b/arch/arm/mach-socfpga/include/mach/reset_manager.h
>> > index 9e253bf..64526b6 100644
>> > --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
>> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
>> > @@ -43,7 +43,9 @@ void socfpga_per_reset_all(void);
>> >  /* Create a human-readable reference to SoCFPGA reset. */
>> >  #define SOCFPGA_RESET(_name)   RSTMGR_##_name
>> >
>> > -#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>> > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>> > +#include 
>> > +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
>> You can use #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) instead to
>> keep
>> this list sorted.
> You want sort with GEN5, ARRIA10 or sorted alphanumerically ARRIA10
> then GEN5?
>>
>> >
>> >  #include 
>> >  #endif
>> >
>> > diff --git a/arch/arm/mach-
>> > socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-
>> > socfpga/include/mach/reset_manager_arria10.h
>> > new file mode 100755
>> > index 000..2668a86
>> > --- /dev/null
>> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
>> > @@ -0,0 +1,144 @@
>> > +/*
>> > + *  Copyright (C) 2012-2017 Altera Corporation 
>> > + *
>> > + * SPDX-License-Identifier:GPL-2.0+
>> > + */
>> > +
>> > +#ifndef_RESET_MANAGER_ARRIA10_H_
>> > +#define_RESET_MANAGER_ARRIA10_H_
>> Use #ifdef[space]FOO and #define[space]FOO
> Okay
>>
>> >
>> > +void watchdog_disable(void);
>> > +void reset_deassert_noc_ddr_scheduler(void);
>> > +int is_wdt_in_reset(void);
>> > +void emac_manage_reset(ulong emacbase, uint state);
>> > +int reset_deassert_bridges_handoff(void);
>> > +void reset_assert_fpga_connected_peripherals(void);
>> > +void reset_deassert_osc1wd0(void);
>> > +void reset_assert_uart(void);
>> > +void reset_deassert_uart(void);
>> [...]
>>
>> >
>> > +#endif /* _RESET_MANAGER_ARRIA10_H_ */
>> > diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c
>> > b/arch/arm/mach-socfpga/reset_manager_arria10.c
>> > new file mode 100644
>> > index 000..01156de
>> > --- /dev/null
>> > +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
>> > @@ -0,0 +1,406 @@
>> > +/*
>> > + * Copyright (C) 2016-2017 Intel Corporation
>> > + *
>> > + * SPDX-License-Identifier:GPL-2.0
>> > + */
>> > +
>> > +#include 
>> > +#include 
>> > +#include 
>> > +#include 
>> > +#include 
>> > +#include 
>> > +#include 
>> > +#include 
>> > +
>> > +DECLARE_GLOBAL_DATA_PTR;
>> > +
>> > +static const struct socfpga_reset_manager *reset_manager_base =
>> > +   (void *)SOCFPGA_RSTMGR_ADDRESS;
>> > +static const struct socfpga_system_manager *sysmgr_regs =
>> > +   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>> Use the tabs consistently, one or two, but pick one.
> Okay.
>>
>> >
>> > +static int get_bridge_init_val(const void *blob, int compat_id);
>> > +
>> > +#define ECC_MASK (ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK|\
>> > +   ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK|\
>> > +   ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK|\
>> > +   ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK|\
>> > +   ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK|\
>> > +   ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK)
>> MSK | \
>>
>> Keep the spacing please.
> Okay.
>>
>> >
>> > +void reset_assert_uart(void)
>> > +{
>> > +   u32 mask = 0;
>> > +   unsigned int com_port;
>> > +
>> > +   com_port = uart_com_port(gd->fdt_blob);
>> What's this function , is it defined later 

Re: [U-Boot] [PATCH 06/20] arm: socfpga: add reset driver support for Arria 10

[Ley Foon Tan]

On Isn, 2017-02-27 at 11:19 +0100, Marek Vasut wrote:
> On 02/27/2017 11:14 AM, Ley Foon Tan wrote:
> > 
> > On Sab, 2017-02-25 at 22:28 +0100, Marek Vasut wrote:
> > > 
> > > On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> > > > 
> > > > 
> > > > Add reset driver support for Arria 10.
> > > > 
> > > > Signed-off-by: Tien Fong Chee 
> > > > Signed-off-by: Ley Foon Tan 
> > > > ---
> > > >  arch/arm/mach-socfpga/Makefile |   2 +
> > > >  arch/arm/mach-socfpga/include/mach/reset_manager.h |   4 +-
> > > >  .../include/mach/reset_manager_arria10.h   | 144
> > > > 
> > > >  arch/arm/mach-socfpga/reset_manager_arria10.c  | 406
> > > > +
> > > >  include/dt-bindings/reset/altr,rst-mgr-a10.h   | 103
> > > > ++
> > > >  5 files changed, 658 insertions(+), 1 deletion(-)
> > > >  create mode 100755 arch/arm/mach-
> > > > socfpga/include/mach/reset_manager_arria10.h
> > > >  create mode 100644 arch/arm/mach-
> > > > socfpga/reset_manager_arria10.c
> > > >  create mode 100644 include/dt-bindings/reset/altr,rst-mgr-
> > > > a10.h
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> > > > socfpga/Makefile
> > > > index e83da2e..d81f003 100644
> > > > --- a/arch/arm/mach-socfpga/Makefile
> > > > +++ b/arch/arm/mach-socfpga/Makefile
> > > > @@ -10,6 +10,8 @@
> > > >  obj-y  += misc.o timer.o reset_manager.o clock_manager.o
> > > > \
> > > >        fpga_manager.o board.o
> > > >  
> > > > +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) +=
> > > > reset_manager_arria10.o
> > > > +
> > > >  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> > > >  
> > > >  # QTS-generated config file wrappers
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > > > b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > > > index 9e253bf..64526b6 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > > > @@ -43,7 +43,9 @@ void socfpga_per_reset_all(void);
> > > >  /* Create a human-readable reference to SoCFPGA reset. */
> > > >  #define SOCFPGA_RESET(_name)   RSTMGR_##_name
> > > >  
> > > > -#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > +#include 
> > > > +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > You can use #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) instead
> > > to
> > > keep
> > > this list sorted.
> > You want sort with GEN5, ARRIA10 or sorted alphanumerically ARRIA10
> > then GEN5?
> I'd opt for sorting this in the order in which those parts came out,
> but
> that might be just my personal preference ...

Okay, will sorting it with GEN5, ARRIA10.

Thanks.

Regards
Ley Foon
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Re: [U-Boot] [PATCH 06/20] arm: socfpga: add reset driver support for Arria 10

[Marek Vasut]

On 02/27/2017 11:14 AM, Ley Foon Tan wrote:
> On Sab, 2017-02-25 at 22:28 +0100, Marek Vasut wrote:
>> On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
>>>
>>> Add reset driver support for Arria 10.
>>>
>>> Signed-off-by: Tien Fong Chee 
>>> Signed-off-by: Ley Foon Tan 
>>> ---
>>>  arch/arm/mach-socfpga/Makefile |   2 +
>>>  arch/arm/mach-socfpga/include/mach/reset_manager.h |   4 +-
>>>  .../include/mach/reset_manager_arria10.h   | 144 
>>>  arch/arm/mach-socfpga/reset_manager_arria10.c  | 406
>>> +
>>>  include/dt-bindings/reset/altr,rst-mgr-a10.h   | 103 ++
>>>  5 files changed, 658 insertions(+), 1 deletion(-)
>>>  create mode 100755 arch/arm/mach-
>>> socfpga/include/mach/reset_manager_arria10.h
>>>  create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
>>>  create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h
>>>
>>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
>>> socfpga/Makefile
>>> index e83da2e..d81f003 100644
>>> --- a/arch/arm/mach-socfpga/Makefile
>>> +++ b/arch/arm/mach-socfpga/Makefile
>>> @@ -10,6 +10,8 @@
>>>  obj-y  += misc.o timer.o reset_manager.o clock_manager.o \
>>>fpga_manager.o board.o
>>>  
>>> +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
>>> +
>>>  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
>>>  
>>>  # QTS-generated config file wrappers
>>> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
>>> b/arch/arm/mach-socfpga/include/mach/reset_manager.h
>>> index 9e253bf..64526b6 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
>>> @@ -43,7 +43,9 @@ void socfpga_per_reset_all(void);
>>>  /* Create a human-readable reference to SoCFPGA reset. */
>>>  #define SOCFPGA_RESET(_name)   RSTMGR_##_name
>>>  
>>> -#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>> +#include 
>>> +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
>> You can use #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) instead to
>> keep
>> this list sorted.
> You want sort with GEN5, ARRIA10 or sorted alphanumerically ARRIA10
> then GEN5?

I'd opt for sorting this in the order in which those parts came out, but
that might be just my personal preference ...

[...]

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 06/20] arm: socfpga: add reset driver support for Arria 10

[Ley Foon Tan]

On Sab, 2017-02-25 at 22:28 +0100, Marek Vasut wrote:
> On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> > 
> > Add reset driver support for Arria 10.
> > 
> > Signed-off-by: Tien Fong Chee 
> > Signed-off-by: Ley Foon Tan 
> > ---
> >  arch/arm/mach-socfpga/Makefile |   2 +
> >  arch/arm/mach-socfpga/include/mach/reset_manager.h |   4 +-
> >  .../include/mach/reset_manager_arria10.h   | 144 
> >  arch/arm/mach-socfpga/reset_manager_arria10.c  | 406
> > +
> >  include/dt-bindings/reset/altr,rst-mgr-a10.h   | 103 ++
> >  5 files changed, 658 insertions(+), 1 deletion(-)
> >  create mode 100755 arch/arm/mach-
> > socfpga/include/mach/reset_manager_arria10.h
> >  create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
> >  create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h
> > 
> > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> > socfpga/Makefile
> > index e83da2e..d81f003 100644
> > --- a/arch/arm/mach-socfpga/Makefile
> > +++ b/arch/arm/mach-socfpga/Makefile
> > @@ -10,6 +10,8 @@
> >  obj-y  += misc.o timer.o reset_manager.o clock_manager.o \
> >        fpga_manager.o board.o
> >  
> > +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
> > +
> >  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> >  
> >  # QTS-generated config file wrappers
> > diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > index 9e253bf..64526b6 100644
> > --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > @@ -43,7 +43,9 @@ void socfpga_per_reset_all(void);
> >  /* Create a human-readable reference to SoCFPGA reset. */
> >  #define SOCFPGA_RESET(_name)   RSTMGR_##_name
> >  
> > -#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +#include 
> > +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
> You can use #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) instead to
> keep
> this list sorted.
You want sort with GEN5, ARRIA10 or sorted alphanumerically ARRIA10
then GEN5?
> 
> > 
> >  #include 
> >  #endif
> >  
> > diff --git a/arch/arm/mach-
> > socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-
> > socfpga/include/mach/reset_manager_arria10.h
> > new file mode 100755
> > index 000..2668a86
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> > @@ -0,0 +1,144 @@
> > +/*
> > + *  Copyright (C) 2012-2017 Altera Corporation 
> > + *
> > + * SPDX-License-Identifier:GPL-2.0+
> > + */
> > +
> > +#ifndef_RESET_MANAGER_ARRIA10_H_
> > +#define_RESET_MANAGER_ARRIA10_H_
> Use #ifdef[space]FOO and #define[space]FOO
Okay
> 
> > 
> > +void watchdog_disable(void);
> > +void reset_deassert_noc_ddr_scheduler(void);
> > +int is_wdt_in_reset(void);
> > +void emac_manage_reset(ulong emacbase, uint state);
> > +int reset_deassert_bridges_handoff(void);
> > +void reset_assert_fpga_connected_peripherals(void);
> > +void reset_deassert_osc1wd0(void);
> > +void reset_assert_uart(void);
> > +void reset_deassert_uart(void);
> [...]
> 
> > 
> > +#endif /* _RESET_MANAGER_ARRIA10_H_ */
> > diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c
> > b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > new file mode 100644
> > index 000..01156de
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > @@ -0,0 +1,406 @@
> > +/*
> > + * Copyright (C) 2016-2017 Intel Corporation
> > + *
> > + * SPDX-License-Identifier:GPL-2.0
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +static const struct socfpga_reset_manager *reset_manager_base =
> > +   (void *)SOCFPGA_RSTMGR_ADDRESS;
> > +static const struct socfpga_system_manager *sysmgr_regs =
> > +   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> Use the tabs consistently, one or two, but pick one.
Okay.
> 
> > 
> > +static int get_bridge_init_val(const void *blob, int compat_id);
> > +
> > +#define ECC_MASK (ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK|\
> > +   ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK|\
> > +   ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK|\
> > +   ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK|\
> > +   ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK|\
> > +   ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK)
> MSK | \
> 
> Keep the spacing please.
Okay.
> 
> > 
> > +void reset_assert_uart(void)
> > +{
> > +   u32 mask = 0;
> > +   unsigned int com_port;
> > +
> > +   com_port = uart_com_port(gd->fdt_blob);
> What's this function , is it defined later in the patchset ?
Oh ya, it is in later patch [misc]. I will try to rearrange this.
> 
> > 
> > +   if (SOCFPGA_UART1_ADDRESS == com_port)
> > +   mask |= ALT_RSTMGR_PER1MODRST_UART1_SET_MSK;
> > 

Re: [U-Boot] [PATCH 06/20] arm: socfpga: add reset driver support for Arria 10

[Marek Vasut]

On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> Add reset driver support for Arria 10.
> 
> Signed-off-by: Tien Fong Chee 
> Signed-off-by: Ley Foon Tan 
> ---
>  arch/arm/mach-socfpga/Makefile |   2 +
>  arch/arm/mach-socfpga/include/mach/reset_manager.h |   4 +-
>  .../include/mach/reset_manager_arria10.h   | 144 
>  arch/arm/mach-socfpga/reset_manager_arria10.c  | 406 
> +
>  include/dt-bindings/reset/altr,rst-mgr-a10.h   | 103 ++
>  5 files changed, 658 insertions(+), 1 deletion(-)
>  create mode 100755 arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
>  create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
>  create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index e83da2e..d81f003 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -10,6 +10,8 @@
>  obj-y+= misc.o timer.o reset_manager.o clock_manager.o \
>  fpga_manager.o board.o
>  
> +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
> +
>  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
>  
>  # QTS-generated config file wrappers
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
> b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> index 9e253bf..64526b6 100644
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> @@ -43,7 +43,9 @@ void socfpga_per_reset_all(void);
>  /* Create a human-readable reference to SoCFPGA reset. */
>  #define SOCFPGA_RESET(_name) RSTMGR_##_name
>  
> -#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#include 
> +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)

You can use #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) instead to keep
this list sorted.

>  #include 
>  #endif
>  
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h 
> b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> new file mode 100755
> index 000..2668a86
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> @@ -0,0 +1,144 @@
> +/*
> + *  Copyright (C) 2012-2017 Altera Corporation 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#ifndef  _RESET_MANAGER_ARRIA10_H_
> +#define  _RESET_MANAGER_ARRIA10_H_

Use #ifdef[space]FOO and #define[space]FOO

> +void watchdog_disable(void);
> +void reset_deassert_noc_ddr_scheduler(void);
> +int is_wdt_in_reset(void);
> +void emac_manage_reset(ulong emacbase, uint state);
> +int reset_deassert_bridges_handoff(void);
> +void reset_assert_fpga_connected_peripherals(void);
> +void reset_deassert_osc1wd0(void);
> +void reset_assert_uart(void);
> +void reset_deassert_uart(void);

[...]

> +#endif /* _RESET_MANAGER_ARRIA10_H_ */
> diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c 
> b/arch/arm/mach-socfpga/reset_manager_arria10.c
> new file mode 100644
> index 000..01156de
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
> @@ -0,0 +1,406 @@
> +/*
> + * Copyright (C) 2016-2017 Intel Corporation
> + *
> + * SPDX-License-Identifier:GPL-2.0
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct socfpga_reset_manager *reset_manager_base =
> + (void *)SOCFPGA_RSTMGR_ADDRESS;
> +static const struct socfpga_system_manager *sysmgr_regs =
> + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;

Use the tabs consistently, one or two, but pick one.

> +static int get_bridge_init_val(const void *blob, int compat_id);
> +
> +#define ECC_MASK (ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK|\
> + ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK|\
> + ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK|\
> + ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK|\
> + ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK|\
> + ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK)

MSK | \

Keep the spacing please.

> +void reset_assert_uart(void)
> +{
> + u32 mask = 0;
> + unsigned int com_port;
> +
> + com_port = uart_com_port(gd->fdt_blob);

What's this function , is it defined later in the patchset ?

> + if (SOCFPGA_UART1_ADDRESS == com_port)
> + mask |= ALT_RSTMGR_PER1MODRST_UART1_SET_MSK;
> + else if (SOCFPGA_UART0_ADDRESS == com_port)
> + mask |= ALT_RSTMGR_PER1MODRST_UART0_SET_MSK;

Use if (foo == VALUE) please, not the other way around. Fix globally.

> + setbits_le32(_manager_base->per1modrst, mask);

You can combine this with the deassert_uart() function and use
clrsetbits instead to avoid duplication of the if () else () logic above.

> +}
> +
> +void reset_deassert_uart(void)
> +{
> + u32 mask = 0;
> + unsigned int com_port;
> +
> + com_port = 

[U-Boot] [PATCH 06/20] arm: socfpga: add reset driver support for Arria 10

[Ley Foon Tan]

Add reset driver support for Arria 10.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/Makefile |   2 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   4 +-
 .../include/mach/reset_manager_arria10.h   | 144 
 arch/arm/mach-socfpga/reset_manager_arria10.c  | 406 +
 include/dt-bindings/reset/altr,rst-mgr-a10.h   | 103 ++
 5 files changed, 658 insertions(+), 1 deletion(-)
 create mode 100755 arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
 create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e83da2e..d81f003 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -10,6 +10,8 @@
 obj-y  += misc.o timer.o reset_manager.o clock_manager.o \
   fpga_manager.o board.o
 
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 9e253bf..64526b6 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -43,7 +43,9 @@ void socfpga_per_reset_all(void);
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)   RSTMGR_##_name
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
+#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
 #endif
 
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
new file mode 100755
index 000..2668a86
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -0,0 +1,144 @@
+/*
+ *  Copyright (C) 2012-2017 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef_RESET_MANAGER_ARRIA10_H_
+#define_RESET_MANAGER_ARRIA10_H_
+
+void watchdog_disable(void);
+void reset_deassert_noc_ddr_scheduler(void);
+int is_wdt_in_reset(void);
+void emac_manage_reset(ulong emacbase, uint state);
+int reset_deassert_bridges_handoff(void);
+void reset_assert_fpga_connected_peripherals(void);
+void reset_deassert_osc1wd0(void);
+void reset_assert_uart(void);
+void reset_deassert_uart(void);
+
+struct socfpga_reset_manager {
+   u32 stat;
+   u32 ramstat;
+   u32 miscstat;
+   u32 ctrl;
+   u32 hdsken;
+   u32 hdskreq;
+   u32 hdskack;
+   u32 counts;
+   u32 mpumodrst;
+   u32 per0modrst;
+   u32 per1modrst;
+   u32 brgmodrst;
+   u32 sysmodrst;
+   u32 coldmodrst;
+   u32 nrstmodrst;
+   u32 dbgmodrst;
+   u32 mpuwarmmask;
+   u32 per0warmmask;
+   u32 per1warmmask;
+   u32 brgwarmmask;
+   u32 syswarmmask;
+   u32 nrstwarmmask;
+   u32 l3warmmask;
+   u32 tststa;
+   u32 tstscratch;
+   u32 hdsktimeout;
+   u32 hmcintr;
+   u32 hmcintren;
+   u32 hmcintrens;
+   u32 hmcintrenr;
+   u32 hmcgpout;
+   u32 hmcgpin;
+};
+
+/*
+ * SocFPGA Arria10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2   RSTMGR_DEFINE(1, 2)
+#define RSTMGR_L4WD0   RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1   RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0   RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1   RSTMGR_DEFINE(2, 17)
+#define RSTMGR_SPIM0   RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1   RSTMGR_DEFINE(1, 18)
+#define RSTMGR_QSPIRSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
+#define RSTMGR_DDRSCH  RSTMGR_DEFINE(3, 6)
+
+#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSKBIT(1)
+#define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSKBIT(0)
+#define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSKBIT(1)
+#define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSKBIT(2)
+#define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK BIT(3)
+#define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK BIT(4)
+#define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK BIT(5)
+#define